Power saving system and method for refreshing a computer memory by switching between interval refresh and self-refresh operations

Claim 2

A computer system comprising: a CPU for providing system operation control signals including normal mode operation instruction and standby mode operation instruction signals; a memory device for storing memory contents, the memory device requiring refreshing at a certain interval cycle; a clock generator for supplying clock timing signals to elements of the system, including the CPU, the clock generator stopping the supply of clock timing signals when the CPU provides the standby mode instruction signal; a memory control means for providing memory operation control signals including at least two kinds of memory refresh instruction signals, one of the kinds of memory refresh instruction signals being an interval refresh signal, to the memory device in accordance with the normal mode and standby mode operation instruction signals from the CPU, the memory control means providing a single first interval refresh signal to the memory device just before the time when the CPU changes from providing the normal mode operation instruction signal to the standby mode operation instruction signal and a single second interval refresh signal provided to the memory device just after the time when the CPU changes from providing the standby mode operation instruction signal to the normal mode operation instruction signal; an interval refreshing means for executing an interval refresh operation of the memory device periodically in accordance with the clock timing signals while the CPU is providing the normal operation mode instruction signal to the memory control means; and a self-refreshing means for executing a self refresh operation of the memory device when the CPU provides the standby mode instruction signal to the memory control means in order to enter a standby mode of system operation.

Claim 3

The computer system according to claim 1, wherein said memory device is a DRAM which has means for discriminating the instruction change between the interval refresh operation and the self-refresh operation and the memory control means is a DRAM controller.

Claim 4

A computer system comprising: a CPU for providing system operation control signals including normal mode operation instruction and standby mode operation instruction signals; a memory device for storing memory contents, the memory device requiring refreshing at a certain interval cycle; a clock generator for supplying clock timing signals to elements of the system including the CPU, a memory control means for providing memory operation control signals including at least two kinds of memory refresh instruction signals, one of the kinds of memory refresh instruction signals being an interval refresh instruction signal, to the memory device in accordance with the normal mode and standby mode operation instruction signals from the CPU, the memory control means providing a single first interval refresh signal to the memory device just before the time when the CPU changes from providing the normal mode operation instruction signal to the standby mode operation instruction signal and a single second interval refresh signal provided to the memory device just after the time when the CPU changes from providing the standby mode operation instruction signal to the normal mode operation instruction signal; and a memory refreshing means for refreshing the memory device in accordance with the refresh instruction signals from the memory control means, wherein the memory refresh means executes an interval refresh operation of the memory device while the CPU provides the normal operation mode instruction signal to the memory control means and the memory refresh means executes a self-refresh operation of the memory device when the CPU provides the standby mode instruction signal to the memory control means and the memory control means instructs the memory refresh means to change memory refresh operation; wherein the clock generator stops supplying the clock timing signals to system elements when the memory device enters the self-refresh operation.

Claim 5

A computer system comprising: a CPU for providing system operation control signals including normal mode operation instruction and standby mode operation instruction signals; a memory device for storing memory contents, the memory device requiring refreshing at a certain interval cycle; a clock generator for supplying clock timing signals to elements of the system including the CPU, a memory control means for providing memory operation control signals including at least two kinds of memory refresh instruction signals, one of the kinds of memory refresh instruction signals being an interval refresh instruction signal, to the memory device in accordance with the normal mode and standby mode operation instruction signals from the CPU, the memory control means providing a single first interval refresh signal to the memory device just before the time when the CPU changes from providing the normal mode operation instruction signal to the standby mode operation instruction signal and a single second interval refresh signal provided to the memory device just after the time when the CPU changes from providing the standby mode operation instruction signal to the normal mode operation instruction signal; and a memory refreshing means for refreshing the memory device in accordance with the refresh instruction signals from the memory control means, wherein the memory refresh means executes an interval refresh operation of the memory device while the CPU provides the normal operation mode instruction signal to the memory control means and the memory refresh means executes a self-refresh operation of the memory device when the CPU provides the standby mode instruction signal to the memory control means and the memory control means instructs the memory refresh means to change memory refresh operation; wherein the clock generator stops supplying the clock timing signals to system elements when the memory device enters the self-refresh operation.

Claim 6

The computer system according to claim 3, wherein said memory device is a DRAM which has means for discriminating the instruction change between the interval refresh operation and the self-refresh operation, and the memory control means is a DRAM controllor.

Claim 7

The computer system according to claim 3, wherein said memory refreshing means comprises: a refresh count means for counting refresh intervals in accordance with the memory refresh instruction signals from the memory control means; and a refresh generator for proving memory refresh execution signals to the memory device in accordance with an output signal of the refresh count means.

Claim 8

The computer system according to claim 4, wherein the memory refreshing means provides CAS before RAS signals to the DRAM, and the DRAM enters the self refresh operation when the CAS and RAS signals are at a low level over a predetermined pulse rise time.

Claim 9

The computer system according to claim 3 or 4, wherein during the interval refresh operation said memory refreshing means provides for a transition of CAS and RAS signals simultaneously from a low level to a high level after a predetermined time interval, the predetermined time interval beginning with the start of the supplying of the timing signals from the clock generator.

Claim 10

A computer system comprising: a CPU for providing system operation control signals including normal mode operation instruction and standby mode operation instruction signals; a memory device for storing memory contents, the memory device requiring refreshing at a certain interval cycle; a clock generator for supplying clock timing signals to elements of the system, including the CPU, the clock generator ceasing to supply the timing signals when the system enters a standby mode of operation; a memory control means for providing memory operation control signals including first and second memory refresh instruction signals, the first memory refresh instruction signal being an interval refresh signal, in response to the normal mode and standby mode operation instruction signals, respectively, the memory control means providing a single first interval refresh signal to the memory device just before the time when the CPU changes from providing the normal mode operation instruction signal to the standby mode operation instruction signal and a single second interval refresh signal provided to the memory device just after the time when the CPU changes from providing the standby mode operation instruction signal to the normal mode operation instruction signal; a standby mode detector for providing a refresh mode change instruction signal to the memory control means in response to the standby mode operation instruction signal, an interval refreshing means for executing an interval refresh operation of the memory device periodically in accordance with the first refresh instruction signal, and a self-refreshing means for executing a self refresh operation of the memory device in accordance with the second refresh instruction signal during the standby mode of system operation.

Claim 11

A computer system comprising: a CPU for providing system operation control signals including normal mode operation instruction and standby mode operation instruction signals; a memory device for storing memory contents, the memory device requiring refreshing at a certain interval cycle; a clock generator for supplying clock timing signals to elements of the system, including the CPU, the clock generator ceasing to supply the timing signals when the system enters a standby mode of operation; a memory control means for providing memory operation control signals including first and second memory refresh instruction signals, the first memory refresh instruction signal being an interval refresh signal, in response to the normal mode and standby mode operation instruction signals, respectively, the memory control means providing a single first interval refresh signal to the memory device just before the time when the CPU changes from providing the normal mode operation instruction signal to the standby mode operation instruction signal and a single second interval refresh signal provided to the memory device just after the time when the CPU changes from providing the standby mode operation instruction signal to the normal mode operation instruction signal; a standby mode detector for providing a refresh mode change instruction signal to the memory control means in response to the standby mode operation instruction signal, an interval refreshing means for executing an interval refresh operation of the memory device periodically in accordance with the first refresh instruction signal, and a self-refreshing means for executing a self refresh operation of the memory device in accordance with the second refresh instruction signal during the standby mode of system operation.

Claim 12

A micro-computer system comprising: a DRAM memory requiring refreshing at a certain cycle to maintain its memory contents; a CPU for providing system operation instruction signals including normal operation mode and standby operation mode instruction signals; a clock generator for supplying clock signals to components of the system, including the CPU; a memory control means for providing memory operation control signals including two kinds of memory refresh signals, one of the kinds of memory refresh instruction signal being an interval refresh signal, to the DRAM memory in accordance with the system operation instruction signals, the memory control means providing a single first interval refresh signal to the DRAM memory just before the time when the CPU changes from providing the normal mode operation instruction signal to the standby mode operation instruction signal and a single second interval refresh signal to the DRAM memory just after the time when the CPU changes from providing the standby mode operation instruction signal to the normal mode operation instruction signal; a detecting means for detecting the standby operation mode signal from the CPU and sending a self refresh operation instruction signal to the memory control means; and a memory refresh means for refreshing the DRAM memory in accordance with the refresh control signal from the memory control means; wherein, the memory refresh means executes an interval refresh operation of the DRAM memory when the CPU provides the normal operation mode instruction signal, the memory refresh means executes a self-refresh operation of the DRAM memory when the CPU provides the standby operation mode instruction signal, and the CPU sends a stop signal to the clock generator when the DRAM memory enters self-refresh operation.

Claim 13

A micro-computer system comprising: a DRAM memory requiring refreshing at a certain cycle to maintain its memory contents; a CPU for providing system operation instruction signals including normal operation mode and standby operation mode instruction signals; a clock generator for supplying clock signals to components of the system, including the CPU; a memory control means for providing memory operation control signals including two kinds of memory refresh signals, one of the kinds of memory refresh instruction signal being an interval refresh signal, to the DRAM memory in accordance with the system operation instruction signals, the memory control means providing a single first interval refresh signal to the DRAM memory just before the time when the CPU changes from providing the normal mode operation instruction signal to the standby mode operation instruction signal and a single second interval refresh signal to the DRAM memory just after the time when the CPU changes from providing the standby mode operation instruction signal to the normal mode operation instruction signal; a detecting means for detecting the standby operation mode signal from the CPU and sending a self refresh operation instruction signal to the memory control means; and a memory refresh means for refreshing the DRAM memory in accordance with the refresh control signal from the memory control means; wherein, the memory refresh means executes an interval refresh operation of the DRAM memory when the CPU provides the normal operation mode instruction signal, the memory refresh means executes a self-refresh operation of the DRAM memory when the CPU provides the standby operation mode instruction signal, and the CPU sends a stop signal to the clock generator when the DRAM memory enters self-refresh operation.

Claim 14

The micro-computer system according to claim 9, wherein said DRAM memory includes means for discriminating a change of the memory refresh means to the self-refresh operation; and the memory control means is a DRAM controllor.

Claim 15

The micro-computer system according to claim 9, wherein said memory refresh means executes a refresh operation by generating a CAS signal before an RAS signal.

Claim 16

The micro-computer system according to claim 11, wherein said memory refresh means executes the interval refresh operation of the DRAM memory by raising the CAS and RAS signals from a low level to a high level at a predetermined time interval while the CPU provides the normal operation mode instruction signal.

Claim 17

The micro-computer system according to claim 11, wherein said memory refresh means executes the self refresh operation of the memory device by keeping the CAS and RAS signals at a low level for more than a predetermined time interval while the CPU provides the standby operation mode instruction signal.