Common memory protection system in a multiprocessor configuration using semaphore-flags stored at complementary addresses for enabling access to the memory

Claim 2

A common memory protection system in an apparatus having a multiprocessor configuration in which a plurality of CPUs are connected to a common RAM via a common bus, the system comprising: a flag control section for outputting two semaphore-flag signals showing each semaphore-flag condition when said CPU checks two semaphore-flags by accessing the corresponding two semaphore-flag addresses that have the complementary address values to each other; and a memory control section that allows a CPU of a plurality of CPUs' to access any address in said common RAM via said common bus when receiving said semaphore-flag signals, both of which indicate that access to said common RAM is enabled, from said flag control section.

Claim 3

A common memory protection system as set forth in claim 1, wherein said flag control section includes a first decoder that outputs two check signals provided by decoding said two semaphore-flag addresses that have the complementary address values to each other, and two flag storage circuits each of which outputs said semaphore-flag signal at the beginning of a reception of said check signal and indicates that access to said common RAM is enabled at the end of the reception of said check signal; and said memory control section includes a second decoder that is enabled by a reception of said semaphore-flag signals, both of which indicate that access to said common RAM is enabled, from said flag control section and outputs access enable signals provided by decoding a memory address received from said CPU via said common bus, to said common RAM.

Claim 4

A common memory protection system as set forth in claim 1, wherein said common RAM is divided into a plurality of tables each of which has said two semaphore-flags accessed by said semaphore-flags addresses having complementary address values to each other and corresponding to respective segment addresses of said tables; said flag control section includes a first decoder that outputs two check addresses provided by decoding said two semaphore-flag addresses that have complementary address values to each other and correspond to respective segment addresses of said tables, and two flag RAMs each of which outputs said semaphore-flag signals corresponding to each table at the beginning of an input of said check address and indicates that access to each table in said common RAM is enabled at the end of the input of said check address; and said memory control section includes a second decoder that is enabled by said semaphore-flag signals, both of which indicate that access to each table in said common RAM is enabled, from said flag RAMs and outputs access enable signals to said tables in said common RAM by decoding a memory address received from said CPU via said common bus.

Claim 5

A common memory protection system as set forth in claim 1, wherein said memory control section further includes a third decoder that outputs an error signal when said CPUs access said common RAM without detection of said semaphore-flag signals, both of which indicate that access to said common RAM is enabled, from said flag control section, and by reception of said error signal said CPUs activate an exception process and halt their operation.

Claim 6

A common memory protection system as set forth in claim 1, wherein said flag control section outputs said two semaphore-flag signals further having respective specific data that have complementary values to each other so as to check for a data bus error.

Claim 7

A common memory protection system as set forth in claim 1, further having an alignment changing section that changes the bus alignment between said CPUs and said common RAM or I/O section when a problem occurs in said common bus.