Error tolerant read-only storage system

Claim 7

A method for operating a read-only store as set forth in claim 3 including the step of storing an error indication field with each word whereby the correct readout of said word may be ascertained.

Claim 8

A method of organizing a read-only store as set forth in claim 4 wherein said last named step includes the step of determining the parity of each data word together with its address location in the read-only store and storing such combined parity indication with said word in said read-only store.

Claim 9

In a read-only storage memory system including a memory address register, memory accessing circuitry, and a memory buffer register wherein said memory is organized such that each word in memory is stored twice, once in true and once in complement form the improvement which comprises: means for checking the contents of the memory buffer register after read out of a word to determine if the word is correct based on an error detection field carried within the word, and means actuable in response to an incorrect determination to cause the complementary data word stored at a different address in the read-only store to be accessed.

Claim 10

In a read-only storage memory system including a memory address register, memory accessing circuitry, and a memory buffer register wherein said memory is organized such that each word in memory is stored twice, once in true and once in complement form the improvement which comprises: means for checking the contents of the memory buffer register after read out of a word to determine if the word is correct based on an error detection field carried within the word, and means actuable in response to an incorrect determination to cause the complementary data word stored at a different address in the read-only store to be accessed.

Claim 11

A read-only store memory system as set forth in claim 6 wherein the data words in true and complement form are stored at addresses which are themselves complementary, and means for causing the complementary form of the data word currently being read out when an incorrect determination is made to cause the memory to access the complement of the address just accessed.

Claim 12

A read-only memory storage system as set forth in claim 7 including means for determining if a data word currently being accessed from memory is in true or complement form and means for signalling this fact to the memory control system.

Claim 13

In an error tolerant read-only storage memory system including a read-only storage memory, a memory address register, memory accessing circuitry, and a memory buffer register, the data being stored in said memory in true and complement form, the address of the complement form of any given data word being itself the complement of the address of the true form of said data word, the improvement which comprises: control means for accessing said memory at a location specified by the contents of said memory address register, error detection means operative in response to said control means for checking the combined content of the memory address register and the memory buffer register subsequent to any data read out operation, said control means including further means to gate the contents of the memory buffer register to the output of said system when it has been determined that ''''no error'''' exists, and means in said control means for causing the current content of the memory address register to be complemented and gated back into said memory address register, means operative in response to said last means to cause the read-only storage memory to be accessed at said complement address means for examining a specified address field of said memory address register subsequent to each readout operation to determine if a current data word being accessed from the read-only storage memory is in true or complement for, and means for continuing said cycle of operation until a given data readout sequence in said read-only storage memory is completed.

Claim 14

In an error tolerant read-only storage memory system including a read-only storage memory, a memory address register, memory accessing circuitry, and a memory buffer register, the data being stored in said memory in true and complement form, the address of the complement form of any given data word being itself the complement of the address of the true form of said data word, the improvement which comprises: control means for accessing said memory at a location specified by the contents of said memory address register, error detection means operative in response to said control means for checking the combined content of the memory address register and the memory buffer register subsequent to any data read out operation, said control means including further means to gate the contents of the memory buffer register to the output of said system when it has been determined that ''''no error'''' exists, and means in said control means for causing the current content of the memory address register to be complemented and gated back into said memory address register, means operative in response to said last means to cause the read-only storage memory to be accessed at said complement address means for examining a specified address field of said memory address register subsequent to each readout operation to determine if a current data word being accessed from the read-only storage memory is in true or complement for, and means for continuing said cycle of operation until a given data readout sequence in said read-only storage memory is completed.