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US5633825A
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Voltage generating circuit in semiconductor integrated circuit
Assignee: Hitachi Ltd
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Filing: 1996-05-22
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Granted: 1997-05-27
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Expires: 2016-05-22
Abstract
Abstract A voltage generating circuit in a semiconductor integrated circuit driven by two sorts of power supply voltages, includes a unit for generating plural sorts of signals; a unit for selecting one of the plural sorts of signals in response to an operation mode of the semiconductor integrated circuit; and a pumping unit for producing either a first predetermined voltage higher than the high power supply voltage among the two sorts of power supply voltages, or a second predetermined voltage lower than the low power supply voltage by a pumping operation based upon the signal selected by the selecting unit.
Inventors
- 👤 Toshiyuki Sakuta
- 👤 Tomohiro Suzuki
- 👤 Yuriko Iizuka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 12:19
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C5/145; G11C5/143
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
191 words
A semiconductor integrated circuit comprising: a first oscillating circuit outputting a first pulse signal having a first frequency; a second oscillating circuit outputting a second pulse signal having a second frequency; a third oscillating circuit outputting a third pulse signal having a third frequency which is lower than said first frequency and is lower than said second frequency; a first selector having a first input terminal coupled to said first oscillating circuit for receiving said first pulse signal, a second input terminal coupled to said third oscillating circuit for receiving said third pulse signal and an output terminal; a second selector having a first input terminal coupled to said second oscillating circuit for receiving said second pulse signal, a second input terminal coupled to said third oscillating circuit for receiving said third pulse signal and an output terminal; a first pumping circuit having an input terminal coupled to said output terminal of said first selector and an output terminal for outputting a first voltage; and a second pumping circuit having an input terminal coupled to said output terminal of said second selector and an output terminal for outputting a second voltage.
Claim 2
Dependent Claim
191 words
A semiconductor integrated circuit comprising: a first oscillating circuit outputting a first pulse signal having a first frequency; a second oscillating circuit outputting a second pulse signal having a second frequency; a third oscillating circuit outputting a third pulse signal having a third frequency which is lower than said first frequency and is lower than said second frequency; a first selector having a first input terminal coupled to said first oscillating circuit for receiving said first pulse signal, a second input terminal coupled to said third oscillating circuit for receiving said third pulse signal and an output terminal; a second selector having a first input terminal coupled to said second oscillating circuit for receiving said second pulse signal, a second input terminal coupled to said third oscillating circuit for receiving said third pulse signal and an output terminal; a first pumping circuit having an input terminal coupled to said output terminal of said first selector and an output terminal for outputting a first voltage; and a second pumping circuit having an input terminal coupled to said output terminal of said second selector and an output terminal for outputting a second voltage.
Claim 3
Dependent Claim
38 words
A semiconductor integrated circuit according to claim 1, wherein said third oscillating circuit outputs said third pulse signal to said second input terminal of said first selector and to said second input terminal of said second selector, constantly.
Claim 4
Dependent Claim
55 words
A semiconductor integrated circuit according to claim 2, wherein said first oscillating circuit outputs said first pulse signal to said first input terminal of said first selector during a predetermined period, and wherein said second oscillating circuit outputs said second pulse signal to said first input terminal of said second selector during another predetermined period.
Claim 5
Dependent Claim
63 words
A semiconductor integrated circuit according to claim 1, wherein said first and second pumping circuits receive a power supply voltage which is a positive potential, wherein said first voltage is a boosted voltage of which absolute value is larger than that of said power supply voltage, wherein said boosted voltage is a positive potential, and wherein said second voltage is a negative voltage.
Claim 6
Dependent Claim
25 words
A semiconductor integrated circuit according to claim 1, wherein said first voltage is a boosted voltage, and wherein said second voltage is a substrate voltage.
Claim 7
Dependent Claim
18 words
A semiconductor integrated circuit according to claim 1, wherein said first and second pumping circuits comprise capacitors, respectively.
Claim 8
Dependent Claim
19 words
A semiconductor integrated circuit according to claim 1, wherein said first frequency is the same as said second frequency.
Claim 9
Dependent Claim
79 words
A semiconductor integrated circuit according to claim 1, further comprising: a memory array having a plurality of dynamic memory cells; a counter circuit receiving said third pulse signal; and a refresh control circuit coupled to said counter circuit and outputting an internal signal when said dynamic memory cells are refreshed, wherein said third oscillating circuit outputs said third pulse signal to said second input terminal of said first selector and said second input terminal of said second selector, constantly.
Claim 10
Dependent Claim
17 words
A semiconductor integrated circuit according to claim 8, wherein said internal signal is an internal RAS signal.
Claim 11
Dependent Claim
40 words
A semiconductor integrated circuit according to claim 1, further comprising a memory array having a plurality of dynamic memory cells, wherein a self refresh cycle of said plurality of dynamic memory cells is determined based on said third pulse signal.
Claim 12
Dependent Claim
30 words
A semiconductor integrated circuit according to claim 1, further comprising an external terminal receiving an external signal, wherein said first pumping circuit is activated in response to said external signal.
Claim 13
Dependent Claim
16 words
A semiconductor integrated circuit according to claim 11, wherein said external signal is a RAS signal.
Claim 14
Dependent Claim
16 words
A semiconductor integrated circuit according to claim 11, wherein said external signal is a CAS signal.
Claim 15
Dependent Claim
21 words
A semiconductor integrated circuit according to claim 11, wherein said second pumping circuit is activated in response to said external signal.
Claim 16
Dependent Claim
25 words
A semiconductor integrated circuit according to claim 14, wherein said first voltage is a boosted voltage, and wherein said second voltage is a substrate voltage.
Claim 17
Dependent Claim
75 words
A semiconductor integrated circuit according to claim 1, further comprising: external terminals receiving a plurality of address signals; and an address signal change detecting circuit for detecting a change in level in at least one of said plurality of address signals, wherein said second pumping circuit is activated in response to a detection by said address signal change detecting circuit of a change in level in at least one of said plurality of address signals.
Claim 18
Dependent Claim
25 words
A semiconductor integrated circuit according to claim 16, wherein said first voltage is a boosted voltage, and wherein said second voltage is a substrate voltage.
Claim 19
Dependent Claim
108 words
A semiconductor integrated circuit comprising: a first oscillating circuit outputting a first signal having a first frequency; a second oscillating circuit outputting a second signal having a second frequency; a third oscillating circuit outputting a third signal having a third frequency which is lower than said first frequency and is lower than said second frequency; a first pumping circuit coupled to an output of said first oscillating circuit and an output of said third oscillating circuit and generating a first voltage; and a second pumping circuit coupled to an output of said second oscillating circuit and an output of said third oscillating circuit and generating a second voltage.
Claim 20
Dependent Claim
108 words
A semiconductor integrated circuit comprising: a first oscillating circuit outputting a first signal having a first frequency; a second oscillating circuit outputting a second signal having a second frequency; a third oscillating circuit outputting a third signal having a third frequency which is lower than said first frequency and is lower than said second frequency; a first pumping circuit coupled to an output of said first oscillating circuit and an output of said third oscillating circuit and generating a first voltage; and a second pumping circuit coupled to an output of said second oscillating circuit and an output of said third oscillating circuit and generating a second voltage.
Claim 21
Dependent Claim
18 words
A semiconductor integrated circuit according to claim 18, wherein said third oscillating circuit outputs said third signal, constantly.
Claim 22
Dependent Claim
35 words
A semiconductor integrated circuit according to claim 19, wherein said first oscillating circuit outputs said first signal during a predetermined period, and wherein said second oscillating circuit outputs said second signal during another predetermined period.
Claim 23
Dependent Claim
63 words
A semiconductor integrated circuit according to claim 18, wherein said first and second pumping circuits receive a power supply voltage which is a positive potential, wherein said first voltage is a boosted voltage of which absolute value is larger than that of said power supply voltage, wherein said boosted voltage is a positive potential, and wherein said second voltage is a negative voltage.
Claim 24
Dependent Claim
25 words
A semiconductor integrated circuit according to claim 18, wherein said first voltage is a boosted voltage, and wherein said second voltage is a substrate voltage.
Claim 25
Dependent Claim
18 words
A semiconductor integrated circuit according to claim 18, wherein said first and second pumping circuits comprise capacitors, respectively.
Claim 26
Dependent Claim
19 words
A semiconductor integrated circuit according to claim 18, wherein said first frequency is the same as said second frequency.
Claim 27
Dependent Claim
59 words
A semiconductor integrated circuit according to claim 18, further comprising: a memory array having a plurality of dynamic memory cells; a counter circuit receiving said third signal; and a refresh control circuit coupled to said counter circuit and outputting an internal signal when said dynamic memory cells are refreshed, wherein said third oscillating circuit outputs said third signal, constantly.
Claim 28
Dependent Claim
17 words
A semiconductor integrated circuit according to claim 25, wherein said internal signal is an internal RAS signal.
Claim 29
Dependent Claim
39 words
A semiconductor integrated circuit according to claim 18, further comprising a memory array having a plurality of dynamic memory cells, wherein a self refresh cycle of said plurality of dynamic memory cells is determined based on said third signal.
Claim 30
Dependent Claim
30 words
A semiconductor integrated circuit according to claim 18, further comprising an external terminal receiving an external signal, wherein said first pumping circuit is activated in response to said external signal.
Claim 31
Dependent Claim
16 words
A semiconductor integrated circuit according to claim 28, wherein said external signal is a RAS signal.
Claim 32
Dependent Claim
16 words
A semiconductor integrated circuit according to claim 28, wherein said external signal is a CAS signal.
Claim 33
Dependent Claim
21 words
A semiconductor integrated circuit according to claim 28, wherein said second pumping circuit is activated in response to said external signal.
Claim 34
Dependent Claim
25 words
A semiconductor integrated circuit according to claim 31, wherein said first voltage is a boosted voltage, and wherein said second voltage is a substrate voltage.
Claim 35
Dependent Claim
75 words
A semiconductor integrated circuit according to claim 18, further comprising: external terminals receiving a plurality of address signals; and an address signal change detecting circuit for detecting a change in level in at least one of said plurality of address signals, wherein said second pumping circuit is activated in response to a detection by said address signal change detecting circuit of a change in level in at least one of said plurality of address signals.
Claim 36
Dependent Claim
25 words
A semiconductor integrated circuit according to claim 33, wherein said first voltage is a boosted voltage, and wherein said second voltage is a substrate voltage.
References Cited (Backward Citations)
JPH03214669A
Cited
US5119337A
Cited
US5124574A
Cited
US5220534A
Cited
US5264808A
Cited
US5329168A
Cited
US5208557A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-26 | 2000-11-25 | 2001-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-26 | 2004-11-25 | 2005-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-26 | 2008-11-25 | 2009-05-27 | $7700.00 | Window Closed / Lapsed |