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US5633822A
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Method of programming a nonvolatile flash-EEPROM memory array using source line switching transistors
Assignee: STMicroelectronics SRL
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Filing: 1995-06-02
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Granted: 1997-05-27
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Expires: 2015-06-02
Abstract
Abstract A method for writing cells in a memory which reduces errors caused by depleted memory array cells being turned on even when not selected. In the method, nonselected bit lines and nonselected word lines are biased so that the threshold voltage of the nonselected cells increases. In particular, the nonselected bit lines are left floating and the nonselected word lines are set to a zero voltage. Appropriate potentials are applied to the selected word line, selected bit line, and selected source line in order to program the selected cell.
Inventors
- 👤 Giovanni Campardo
- 👤 Giuseppe Crisenza
- 👤 Marco Dallabora
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:30
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; G11C16/06; G11C16/30
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
93 words
A method for writing a flash-EEPROM memory array having a plurality of memory cells, comprising the steps of: setting a selected word line to a first predetermined voltage, setting a selected bit line to a second predetermined voltage less than said first predetermined voltage; leaving nonselected bit lines floating; setting nonselected word lines to a zero voltage; and setting a source line corresponding to a selected memory cell which is connected to the selected bit line and the selected word line to a third predetermined voltage between said first and second predetermined voltages.
Claim 2
Independent Claim
93 words
A method for writing a flash-EEPROM memory array having a plurality of memory cells, comprising the steps of: setting a selected word line to a first predetermined voltage, setting a selected bit line to a second predetermined voltage less than said first predetermined voltage; leaving nonselected bit lines floating; setting nonselected word lines to a zero voltage; and setting a source line corresponding to a selected memory cell which is connected to the selected bit line and the selected word line to a third predetermined voltage between said first and second predetermined voltages.
Claim 3
Dependent Claim
40 words
A method as claimed in claim 1, further comprising the step of connecting each source line to a pass transistor for selectively applying a voltage to said source line, each pass transistor having a gate connected to a word line.
Claim 4
Dependent Claim
37 words
The method of claim 1, wherein said first predetermined voltage is approximately twelve volts, said second predetermined voltage is approximately two volts, and said third predetermined voltage is approximately in the range of six to seven volts.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-26 | 2000-11-25 | 2001-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-26 | 2004-11-25 | 2005-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-26 | 2008-11-25 | 2009-05-27 | $7700.00 | Window Closed / Lapsed |