US5633812A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fault simulation of testing for board circuit failures
Assignee: International Business Machines Corp
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Filing: 1992-09-29
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Granted: 1997-05-27
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Expires: 2012-09-29
Abstract
Abstract A method of accurately simulating how design defects and faults are detected in the board design and manufacturing test environments is provided which uses statements in the simulation control language of a fault simulator. The simulation of the operation of electronic boards (which may not yet have been built) in their expected test environments is possible. The set of statements used in the simulation language allows the proposed functional self-test code, also called diagnostic code or power-on self-test code, which is to be executed by a (micro-)processor, to be tested for its effectiveness. The simulation must synchronize the simulated execution of the processor code to be evaluated with the fault detection by the code being evaluated, simulate the use of any attached tester, such as a logic analyzer, and provide data that can be used for programming devices in the test environment. The PROBE statements in the simulation language determine when the simulator starts and ends a measurement window during which faults can be detected by the simulator. These statements can be used to simulate the amount of time a net must remain stable for test equipment to capture its value.
Inventors
- 👤 James S. Allen
- 👤 Theresa L. Meyer
- 👤 Kenneth D. Wagner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 03:58
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318342
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
118 words
A method of simulating detection of faults in a digital circuit comprising the steps of: defining a logical probe for nets to be measured, for conditions to be satisfied before a measurement of the nets can be made, and for providing a duration of a time-limited measurement window during which said measurement takes place; simulating operation of the circuit for fault-free and faulty operation; monitoring for a satisfaction of the defined conditions to be satisfied before measurement can be made; measuring net values for the nets to be measured upon the satisfaction of the defined conditions during fault-free and faulty operation of the circuit; and recording a fault-free value and a list of faults which can be detected.
Claim 2
Independent Claim
118 words
A method of simulating detection of faults in a digital circuit comprising the steps of: defining a logical probe for nets to be measured, for conditions to be satisfied before a measurement of the nets can be made, and for providing a duration of a time-limited measurement window during which said measurement takes place; simulating operation of the circuit for fault-free and faulty operation; monitoring for a satisfaction of the defined conditions to be satisfied before measurement can be made; measuring net values for the nets to be measured upon the satisfaction of the defined conditions during fault-free and faulty operation of the circuit; and recording a fault-free value and a list of faults which can be detected.
Claim 3
Dependent Claim
35 words
The method of claim 1 further comprising the steps of detecting changes in a net value during the measurement window and recording any indication of change of value together with a corresponding fault being simulated.
Claim 4
Dependent Claim
44 words
The method of claim 1 further comprising the step of creating data from the logical probe for use in programming devices in a test environment to ensure that similar defects, if present, will be detected in the test environment as predicted by the simulation.
Claim 5
Independent Claim
158 words
A method of simulating detection of faults in a digital circuit having functional self test code run by a processor in the circuit comprising the steps of: defining a logical probe for nets to be measured, for conditions to be satisfied before a measurement of the nets can be made, and for providing a duration of a time-limited measurement window during which said measurement takes place; simulating operation of the circuit including operation of the self test code for fault-free and a plurality of fault conditions; monitoring for a satisfaction of the defined conditions to be satisfied before measurement can be made; measuring values for the nets to be measured upon the satisfaction of the defined conditions during fault-free and faulty operation of the circuit; comparing a fault-free net value to the net values measured for each of the faults simulated; recording the fault-free value; and recording values different from the fault-free value together with a corresponding fault.
Claim 6
Independent Claim
158 words
A method of simulating detection of faults in a digital circuit having functional self test code run by a processor in the circuit comprising the steps of: defining a logical probe for nets to be measured, for conditions to be satisfied before a measurement of the nets can be made, and for providing a duration of a time-limited measurement window during which said measurement takes place; simulating operation of the circuit including operation of the self test code for fault-free and a plurality of fault conditions; monitoring for a satisfaction of the defined conditions to be satisfied before measurement can be made; measuring values for the nets to be measured upon the satisfaction of the defined conditions during fault-free and faulty operation of the circuit; comparing a fault-free net value to the net values measured for each of the faults simulated; recording the fault-free value; and recording values different from the fault-free value together with a corresponding fault.
Claim 7
Dependent Claim
35 words
The method of claim 4 further comprising the steps of detecting changes in the net value during the measurement window and recording any indication of change of value together with a corresponding fault being simulated.
Claim 8
Dependent Claim
122 words
Apparatus for simulating detection of faults in a digital circuit comprising: simulator means for simulating circuit operation during fault-free and faulty operation; means for defining a logical probe for nets to be measured, for conditions to be satisfied before a measurement of the nets can be made, and for providing a duration of a time-limited measurement window during which said measurement takes place; means for monitoring for a satisfaction of the defined conditions to be satisfied before measurement can be made; means for measuring values for the nets to be measured upon the satisfaction of the defined conditions during fault-free and faulty operation of the circuit; and means for recording a fault-free value and a list of faults which can be detected.
Claim 9
Dependent Claim
122 words
Apparatus for simulating detection of faults in a digital circuit comprising: simulator means for simulating circuit operation during fault-free and faulty operation; means for defining a logical probe for nets to be measured, for conditions to be satisfied before a measurement of the nets can be made, and for providing a duration of a time-limited measurement window during which said measurement takes place; means for monitoring for a satisfaction of the defined conditions to be satisfied before measurement can be made; means for measuring values for the nets to be measured upon the satisfaction of the defined conditions during fault-free and faulty operation of the circuit; and means for recording a fault-free value and a list of faults which can be detected.
Claim 10
Dependent Claim
43 words
The apparatus of claim 6 further comprising means for creating data from the logical probe for use in programming devices in a test environment to ensure that similar defects, if present, will be detected in the test environment as predicted by the simulation.
Claim 11
Dependent Claim
167 words
Apparatus for simulating detection of faults in a digital circuit having functional self test code run by a processor in the circuit comprising the steps of: means for defining a logical probe for nets to be measured, for conditions to be satisfied before a measurement of the nets can be made, and for providing a duration of a time-limited measurement window during which said measurement takes place; means for simulating operation of the circuit including operation of the self test code for fault-free and a plurality of fault conditions; means for monitoring a satisfaction of the defined conditions to be satisfied before measurement can be made; means for measuring values of the nets upon the satisfaction of the defined conditions during fault-free and faulty operation of the circuit; means for comparing a fault-free net value to the net values measured for each of the faults simulated; means for recording the fault-free value; and means for recording values different from the fault-free value together with a corresponding fault.
Claim 12
Dependent Claim
167 words
Apparatus for simulating detection of faults in a digital circuit having functional self test code run by a processor in the circuit comprising the steps of: means for defining a logical probe for nets to be measured, for conditions to be satisfied before a measurement of the nets can be made, and for providing a duration of a time-limited measurement window during which said measurement takes place; means for simulating operation of the circuit including operation of the self test code for fault-free and a plurality of fault conditions; means for monitoring a satisfaction of the defined conditions to be satisfied before measurement can be made; means for measuring values of the nets upon the satisfaction of the defined conditions during fault-free and faulty operation of the circuit; means for comparing a fault-free net value to the net values measured for each of the faults simulated; means for recording the fault-free value; and means for recording values different from the fault-free value together with a corresponding fault.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-26 | 2000-11-25 | 2001-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-26 | 2004-11-25 | 2005-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-26 | 2008-11-25 | 2009-05-27 | $7700.00 | Window Closed / Lapsed |