US5633785A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit component package with integral passive component
Assignee: University of Southern California
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Filing: 1994-12-30
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Granted: 1997-05-27
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Expires: 2014-12-30
Abstract
Abstract A high-performance, high-density integrated circuit component package includes an IC chip having a plurality of IC bond pads and an interconnect substrate overlying the IC chip. The interconnect substrate includes a plurality of I/O surface pads arrayed across a surface of the interconnect substrate. The I/O surface pads are electrically connected to the IC bond pads via a plurality of traces internal to the interconnect substrate. The interconnect substrate further includes at least one layer comprising capacitive, resistive or inductive material integrally formed therein.
Inventors
- 👤 Robert H. Parker
- 👤 Richard J. Pommer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 18:08
CPC Classifications
H; H10; H10W; H10W90/00; H10W44/00; H10W44/601; H10W70/00; H10W70/60; H10W70/62; H10W70/63; H10W70/635; H10W74/00; H10W74/10; H10W74/131; H10W70/65; H10W70/654; H10W70/655; H10W72/00; H10W72/50; H10W72/521; H10W72/522; H10W72/531; H10W72/5363; H10W72/551; H10W72/552; H10W72/5522; H10W72/851; H10W72/853; H10W72/865; H10W72/874; H10W72/884; H10W90/701; H10W90/731; H10W90/734; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
193 words
A high-performance, high-density integrated circuit (IC) component package comprising: an IC chip having a plurality of IC bond pads extending along an outer periphery of said IC chip; an interconnect substrate bonded to said IC chip with a die attach, said interconnect substrate being mounted as an integral part of the component package and providing structural support to the component package, said interconnect substrate including: a plurality of I/O surface pads arrayed across a surface of said interconnect substrate, said I/O surface pads being electrically connected to said IC bond pads via a plurality of traces internal to said interconnect substrate; at least one layer comprising capacitive, resistive or inductive material integrally formed within said interconnect substrate, said at least one layer comprising capacitive material having a capacitance between 20 pF and 0.1 μF, said at least one layer comprising resistive material having a resistance between 25Ω and 200 kΩ, said at least one layer comprising inductive material having an inductance between 1 nH and 1,000 nH; and distinguishable power and ground planes integrally formed within said interconnect substrate; and a plurality of wire bonds between said traces and said IC bond pads.
Claim 2
Dependent Claim
193 words
A high-performance, high-density integrated circuit (IC) component package comprising: an IC chip having a plurality of IC bond pads extending along an outer periphery of said IC chip; an interconnect substrate bonded to said IC chip with a die attach, said interconnect substrate being mounted as an integral part of the component package and providing structural support to the component package, said interconnect substrate including: a plurality of I/O surface pads arrayed across a surface of said interconnect substrate, said I/O surface pads being electrically connected to said IC bond pads via a plurality of traces internal to said interconnect substrate; at least one layer comprising capacitive, resistive or inductive material integrally formed within said interconnect substrate, said at least one layer comprising capacitive material having a capacitance between 20 pF and 0.1 μF, said at least one layer comprising resistive material having a resistance between 25Ω and 200 kΩ, said at least one layer comprising inductive material having an inductance between 1 nH and 1,000 nH; and distinguishable power and ground planes integrally formed within said interconnect substrate; and a plurality of wire bonds between said traces and said IC bond pads.
Claim 3
Dependent Claim
26 words
The high-performance, high-density IC component package of claim 1 wherein said at least one layer includes a capacitive layer formed between said power and ground planes.
Claim 4
Dependent Claim
23 words
The high-performance, high-density IC component package of claim i wherein said at least one layer includes a capacitive layer forming a discrete capacitor.
Claim 5
Dependent Claim
22 words
The high-performance, high-density IC component package of claim 3 wherein said discrete capacitor is formed between two of said I/O surface pads.
Claim 6
Dependent Claim
31 words
The high-performance, high-density IC component package of claim 1 wherein said at least one layer includes a resistive element formed between said ground plane and one of said I/O surface pads.
Claim 7
Dependent Claim
23 words
The high-performance, high-density IC component package of claim 1 wherein said at least one layer includes a resistive layer forming a discrete resistor.
Claim 8
Dependent Claim
22 words
The high-performance, high-density IC component package of claim 6 wherein said discrete resistor is formed between two of said I/O surface pads.
Claim 9
Dependent Claim
55 words
The high-performance, high-density IC component package of claim 1 wherein said interconnect substrate comprises: an alumina substrate formed over said IC chip; and a multilayer area interconnect formed over said alumina substrate, said multilayer area interconnect including said plurality of I/O surface pads, said surface, said plurality of traces and said at least one layer.
Claim 10
Dependent Claim
30 words
The high-performance, high-density IC component package of claim 1 further comprising: a plurality of solder bumps electrically connected to said plurality of I/O surface pads to facilitate flip chip attachment.
Claim 11
Dependent Claim
157 words
A high-performance, high-density integrated circuit (IC) component package comprising: an IC chip having a plurality of IC bond pads; and an interconnect substrate bonded to said IC chip with a die attach, said interconnect substrate being mounted as an integral part of the component package and providing structural support to the component package, said interconnect substrate including: a plurality of I/O surface pads arrayed across a surface of said interconnect substrate, said I/O surface pads being electrically connected to said IC bond pads via a plurality of traces internal to said interconnect substrate; and at least one layer comprising capacitive, resistive or inductive material integrally formed within said interconnect substrate, said at least one layer comprising capacitive material having a capacitance of at least 20 pF, said at least one layer comprising resistive material having a resistance of at least 25Ω, said at least one layer comprising inductive material having an inductance of at least 1 nH.
Claim 12
Dependent Claim
157 words
A high-performance, high-density integrated circuit (IC) component package comprising: an IC chip having a plurality of IC bond pads; and an interconnect substrate bonded to said IC chip with a die attach, said interconnect substrate being mounted as an integral part of the component package and providing structural support to the component package, said interconnect substrate including: a plurality of I/O surface pads arrayed across a surface of said interconnect substrate, said I/O surface pads being electrically connected to said IC bond pads via a plurality of traces internal to said interconnect substrate; and at least one layer comprising capacitive, resistive or inductive material integrally formed within said interconnect substrate, said at least one layer comprising capacitive material having a capacitance of at least 20 pF, said at least one layer comprising resistive material having a resistance of at least 25Ω, said at least one layer comprising inductive material having an inductance of at least 1 nH.
Claim 13
Dependent Claim
50 words
The high-performance, high-density IC component package of claim 10 wherein said I/O surface pads are positioned on said surface such that a spacing between said I/O surface pads is substantially greater than a spacing between said IC bond pads for easier coupling of said IC component package to external circuitry.
Claim 14
Dependent Claim
26 words
The high-performance, high-density IC component package of claim 10 wherein said interconnect substrate has an area substantially the same as an area of said IC chip.
Claim 15
Dependent Claim
24 words
The high-performance, high-density IC component package of claim 10 further wherein said interconnect substrate further comprises distinguishable power and ground planes integrally formed therein.
Claim 16
Dependent Claim
26 words
The high-performance, high-density IC component package of claim 13 wherein said at least one layer includes a capacitive layer formed between said power and ground planes.
Claim 17
Dependent Claim
23 words
The high-performance, high-density IC component package of claim 10 wherein said at least one layer includes a capacitive layer forming a discrete capacitor.
Claim 18
Dependent Claim
22 words
The high-performance, high-density IC component package of claim 15 wherein said discrete capacitor is formed between two of said I/O surface pads.
Claim 19
Dependent Claim
45 words
The high-performance, high-density IC component package of claim 10: wherein said interconnect substrate further comprises a distinguishable ground plane integrally formed therein; and wherein said at least one layer includes a resistive element formed between said ground plane and one of said I/O surface pads.
Claim 20
Dependent Claim
23 words
The high-performance, high-density IC component package of claim 10 wherein said at least one layer includes a resistive layer forming a discrete resistor.
Claim 21
Dependent Claim
22 words
The high-performance, high-density IC component package of claim 18 wherein said discrete resistor is formed between two of said I/O surface pads.
Claim 22
Dependent Claim
55 words
The high-performance, high-density IC component package of claim 10 wherein said interconnect substrate comprises: an alumina substrate formed over said IC chip; and a multilayer area interconnect formed over said alumina substrate, said multilayer area interconnect including said plurality of I/O surface pads, said surface, said plurality of traces and said at least one layer.
Claim 23
Dependent Claim
30 words
The high-performance, high-density IC component package of claim 10 further comprising: a plurality of solder bumps electrically connected to said plurality of I/O surface pads to facilitate flip chip attachment.
Claim 24
Dependent Claim
24 words
The high-performance, high-density IC component package of claim 10 further comprising: a plurality of wire bonds between said traces and said IC bond pads.
Claim 25
Dependent Claim
22 words
The high-performance, high-density IC component package of claim 22 further comprising: an environmental encapsulant material applied over said plurality of wire bonds.
Claim 26
Independent Claim
111 words
A method of manufacturing a high-performance, high-density integrated circuit (IC) component package comprising the steps of: (a) providing an IC chip having a plurality of IC bond pads; (b) separately manufacturing an interconnect substrate including at least one layer comprising capacitive, resistive or inductive material integrally formed within the interconnect substrate, said interconnect substrate including a plurality of I/O surface pads arrayed across a surface of the interconnect substrate and a plurality of traces internal to the interconnect substrate; (c) thereafter bonding said interconnect substrate to said IC chip with a die attach; and (d) electrically connecting said I/O surface pads to said IC bond pads via said plurality of traces.
Claim 27
Independent Claim
111 words
A method of manufacturing a high-performance, high-density integrated circuit (IC) component package comprising the steps of: (a) providing an IC chip having a plurality of IC bond pads; (b) separately manufacturing an interconnect substrate including at least one layer comprising capacitive, resistive or inductive material integrally formed within the interconnect substrate, said interconnect substrate including a plurality of I/O surface pads arrayed across a surface of the interconnect substrate and a plurality of traces internal to the interconnect substrate; (c) thereafter bonding said interconnect substrate to said IC chip with a die attach; and (d) electrically connecting said I/O surface pads to said IC bond pads via said plurality of traces.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-26 | 2000-11-25 | 2001-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-26 | 2004-11-25 | 2005-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-26 | 2008-11-25 | 2009-05-27 | $7700.00 | Window Closed / Lapsed |