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US5633783A Expired / Lapsed US ⏱️ 0.0 years remaining

Multi-chip ceramic module for mounting electric parts on both substrate and cap connected through interconnecting pins

Assignee: Fujitsu Ltd
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Filing: 1995-09-29
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Granted: 1997-05-27
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Expires: 2015-09-29
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Abstract

Abstract Multi-layer wiring structures are respectively formed in upper and lower ceramic substrates for electric parts, and interconnecting pins held in contact with contact pads establish electrical connections between the multi-layer wiring structures so as to prevent a multi-chip module from an undesirable disconnection between the multi-layer wiring structures.

Inventors

  • 👤 Takesi Yamamoto

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 08:20
CPC Classifications
H; H10; H10W; H10W72/00; H10W70/00; H10W70/60; H10W70/611; H10W90/00; H10W90/401; H10W72/071; H10W72/075; H10W72/07551; H10W72/07554; H10W72/50; H10W72/541; H10W72/547; H10W90/701; H10W90/751; H10W90/754

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 416 words
A multi-chip module comprising: a first insulating substrate having a first surface, a second surface reverse to said first surface and an inner surface forming a hollow space open to said second surface, said hollow space having a first hollow sub-space open to said second surface and a second hollow sub-space narrower than said first hollow sub-space and contiguous to a central area of said first hollow sub-space; a second insulating substrate having a third surface and a fourth surface reverse to said third surface, said third surface being connected to said second surface so as to close said hollow space therebetween; a first wiring means formed at said first insulating substrate and having portions exposed to said second surface and portions exposed at said hollow space; a second wiring means formed at said second insulating substrate and having portions exposed to said third surface and portions exposed to said fourth surface; some of said portions of said first and second wiring means including contact pads; at least one first electric part accommodated in said second hollow sub-space and electrically connected to said portions of said first wiring means exposed at said hollow space; a plurality of input-and-output means provided on said fourth surface and connected to said portions of said second wiring means exposed to said fourth surface; a plurality of conductive connecting means connected between said portions of said first wiring means exposed to said second surface and said portions of said second wiring means exposed to said third surface, said conductive connecting means including a plurality of interconnecting pins soldered to one of said first wiring means having portions exposed to said second surface and said second wiring means having portions exposed to one of said second surface and said third surface and respectively held in contact with respective contact pads of the other of said first wiring means and said second wiring means, one of said first insulating substrate and said second insulating substrate having a plurality of holes open to one of said third surface and said second surface, said respective contact pads being mounted in respective ones of said plurality of holes, said plurality of interconnecting pins being respectively inserted into said plurality of holes so as to be held in contact with said contact pads mounted in said plurality of holes, respectively; and at least one second electric part mounted on said third surface and connected to said portions of said second wiring means exposed to said third surface.
Claim 2
Dependent Claim 416 words
A multi-chip module comprising: a first insulating substrate having a first surface, a second surface reverse to said first surface and an inner surface forming a hollow space open to said second surface, said hollow space having a first hollow sub-space open to said second surface and a second hollow sub-space narrower than said first hollow sub-space and contiguous to a central area of said first hollow sub-space; a second insulating substrate having a third surface and a fourth surface reverse to said third surface, said third surface being connected to said second surface so as to close said hollow space therebetween; a first wiring means formed at said first insulating substrate and having portions exposed to said second surface and portions exposed at said hollow space; a second wiring means formed at said second insulating substrate and having portions exposed to said third surface and portions exposed to said fourth surface; some of said portions of said first and second wiring means including contact pads; at least one first electric part accommodated in said second hollow sub-space and electrically connected to said portions of said first wiring means exposed at said hollow space; a plurality of input-and-output means provided on said fourth surface and connected to said portions of said second wiring means exposed to said fourth surface; a plurality of conductive connecting means connected between said portions of said first wiring means exposed to said second surface and said portions of said second wiring means exposed to said third surface, said conductive connecting means including a plurality of interconnecting pins soldered to one of said first wiring means having portions exposed to said second surface and said second wiring means having portions exposed to one of said second surface and said third surface and respectively held in contact with respective contact pads of the other of said first wiring means and said second wiring means, one of said first insulating substrate and said second insulating substrate having a plurality of holes open to one of said third surface and said second surface, said respective contact pads being mounted in respective ones of said plurality of holes, said plurality of interconnecting pins being respectively inserted into said plurality of holes so as to be held in contact with said contact pads mounted in said plurality of holes, respectively; and at least one second electric part mounted on said third surface and connected to said portions of said second wiring means exposed to said third surface.
Claim 3
Dependent Claim 44 words
The multi-chip module as set forth in claim 1, further comprising a heat-conductive radiator plate bonded to said at least one electric part and fixed to said first insulating substrate for retaining said at least one first electric part in said second hollow sub-space.
Claim 4
Dependent Claim 20 words
The multi-chip module as set forth in claim 2, further comprising a heat sink bonded to said heat-conductive radiator plate.
Claim 5
Dependent Claim 46 words
The multi-chip module as set forth in claim 1, in which a bottom surface and an inner wall define each of said plurality of holes, and one of said plurality of contact pads covers said bottom surface and at least a part of said inner wall.
Claim 6
Dependent Claim 45 words
The multi-chip module as set forth in claim 1, in which a through-hole is formed in said second insulating substrate, and one of said plurality of interconnecting pins projects through said through-hole so as to serve as a pin for an input or output signal.
Claim 7
Dependent Claim 42 words
The multi-chip module as set forth in claim 1, further comprising an insulating frame bonded to said third surface of said second insulating substrate so as to prevent said at least one second electric part from a damage during an assembling work.
Claim 8
Dependent Claim 60 words
The multi-chip module as set forth in claim 6, in which said insulating frame has an outer surface corresponding to at least a part of said inner surface of said first insulating substrate defining a part of said first hollow sub-space so as to guide said first insulating substrate during an assembling work on said first and second insulating substrates.

References Cited (Backward Citations)

US4724472A Cited
JPH01308057A Cited
US5043794A Cited
JPH04177870A Cited
US5199164A Cited
US5444296A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-05-26 2000-11-25 2001-05-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-05-26 2004-11-25 2005-05-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-05-26 2008-11-25 2009-05-27 $7700.00 Window Closed / Lapsed

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