Scan flip-flop that holds state during shifting

Claim 2

A scan flip-flop circuit that holds state during scan shifting, the scan flip-flop circuit comprising: a multiplexer stage that responds to a logic state of a test enable control signal by providing a normal data input signal received at a normal data input node as the multiplexer stage output when the test enable control signal is in an inactive logic state and by providing a scan data input signal received at a scan input node as the multiplexer stage output when the test enable control signal is in an active logic state; a master latch stage connected to receive and store the multiplexer stage output on periodic transitions of a clock signal provided to the master latch stage; a slave latch stage that includes a slave latch gating element connected to the master latch stage and responsive to the test enable control signal such that a data value stored in the master latch stage is provided from a master latch output node to the slave latch stage on periodic transitions of the clock signal when the test enable control signal is in the inactive logic state and is blocked from the slave latch stage when the test enable control signal is in the active logic state; and a dynamic scan latch element that passes data value stored in the master latch stage to a scan data output of the scan flip-flop circuit on periodic transitions of the clock signal when the test enable control signal is in the active logic state.

Claim 3

A scan flip-flop circuit as in claim 1 wherein the multiplexer stage comprises: a multiplexer inverter element that receives the test enable control signal and provides the complement of the test enable control signal at its output; a first multiplexer pass gate that includes a first n-channel multiplexer transistor having its gate connected to receive the test enable control signal and its source/drain regions connected between the normal data input node and the multiplexer stage output, and a first p-channel multiplexer transistor having its gate connected to receive the complement of the test enable control signal and its source/drain regions connected between the normal data input node and the multiplexer stage output; and a second multiplexer pass gate that includes a second n-channel multiplexer transistor having its gate connected to receive the complement of the test enable control signal and its source/drain regions connected between the scan data input node and the multiplexer stage output, and a second p-channel multiplexer transistor having its gate connected to receive the test enable control signal and its source/drain regions connected between the scan data input node and the multiplexer stage output.

Claim 4

A scan flip-flop circuit that holds state during scan shifting, the scan flip-flop circuit comprising: (a) a multiplexer stage that responds to a logic state of a test enable control signal by providing a normal data input signal received at a normal data input node as the multiplexer stage output when the test enable control signal is in an inactive logic state and by providing a scan data input signal received at a scan input node as the multiplexer stage output when the test enable control signal is in an active logic state; (b) a master latch stage connected to receive and store the multiplexer stage output on periodic transitions of a clock signal provided to the master latch stage; (c) a slave latch stage that includes a slave latch gating element connected to the master latch stage and responsive to the test enable control signal such that a data value stored in the master latch stage is provided from a master latch output node to the slave latch stage on periodic transitions of the clock signal when the test enable control signal is in the inactive logic state and is blocked from the slave latch stage when the test enable control signal is in the active logic state; and (d) a dynamic scan latch element that passes data value stored in the master latch stage to a scan data output of the scan flip-flop circuit on periodic transitions of the clock signal when the test enable control signal is in the active logic state, the dynamic scan latch element including: (i) a scan latch inverter having its output connected to the scan data output of the scan flip-flop circuit; and (ii) a scan latch pass gate that includes a n-channel scan latch transistor having its gate connected to receive the clock signal and its source/drain regions connected between the output of the master latch output node and the input of the scan latch inverter, and a p-channel scan latch transistor having its gate connected to receive the complement of the clock signal and its source/drain regions connected between the output of the master latch output node and the input of the scan latch inverter.

Claim 5

A scan flip-flop circuit that holds state during scan shifting, the scan flip-flop circuit comprising: (a) a multiplexer stage that responds to a logic state of a test enable control signal by providing a normal data input signal received at a normal data input node as the multiplexer stage output when the test enable control signal is in an inactive logic state and by providing a scan data input signal received at a scan input node as the multiplexer stage output when the test enable control signal is in an active logic state; (b) a master latch stage connected to receive and store the multiplexer stage output on periodic transitions of a clock signal provided to the master latch stage; (c) a slave latch stage that includes a slave latch gating element connected to the master latch stage and responsive to the test enable control signal such that a data value stored in the master latch stage is provided from a master latch output node to the slave latch stage on periodic transitions of the clock signal when the test enable control signal is in the inactive logic state and is blocked from the slave latch stage when the test enable control signal is in the active logic state; and (d) a dynamic scan latch element that passes data value stored in the master latch stage to a scan data output of the scan flip-flop circuit on periodic transitions of the clock signal when the test enable control signal is in the active logic state, the dynamic scan latch element including: (i) a scan latch inverter having its output connected to the scan data output of the scan flip-flop circuit; and (ii) a scan latch pass gate that includes a n-channel scan latch transistor having its gate connected to receive the clock signal and its source/drain regions connected between the output of the master latch output node and the input of the scan latch inverter, and a p-channel scan latch transistor having its gate connected to receive the complement of the clock signal and its source/drain regions connected between the output of the master latch output node and the input of the scan latch inverter.

Claim 6

A scan flip-flop circuit that holds state during scan shifting, the scan flip-flop circuit comprising: (a) a multiplexer stage that responds to a logic state of a test enable control signal by providing a normal data input signal received at a normal data input node as the multiplexer stage output when the test enable control signal is in an inactive logic state and by providing a scan data input signal received at a scan input node as the multiplexer stage output when the test enable control signal is in an active logic state, the multiplexer stage including: (i) a multiplexer inverter element that receives the test enable control signal and provides the complement of the test enable control signal at its output; (ii) a first multiplexer pass gate that includes a first n-channel multiplexer transistor having its gate connected to receive the test enable control signal and its source/drain regions connected between the normal data input node and the multiplexer stage output, and a first p-channel multiplexer transistor having its gate connected to receive the complement of the test enable control signal and its source/drain regions connected between the normal data input node and the multiplexer stage output; and (iii) a second multiplexer pass gate that includes a second n-channel multiplexer transistor having its gate connected to receive the complement of the test enable control signal and its source/drain regions connected between the scan data input node and the multiplexer stage output, and a second p-channel multiplexer transistor having its gate connected to receive the test enable control signal and its source/drain regions connected between the scan data input node and the multiplexer stage output; (b) a master latch stage connected to receive and store the multiplexer stage output on periodic transitions of a clock signal provided to the master latch stage; the master latch stage comprises: (i) a first master latch inverter connected to receive the clock signal and to provide the complement of the clock signal at its output; (ii) first and second master pass gate nodes; (iii) a first master latch pass gate that includes a first n-channel master latch transistor having its gate connected to receive the complement of the clock signal and its source/drain regions connected between the multiplexer stage output and the first master pass gate node, and a first p-channel master latch transistor having its gate connected to receive the clock signal and its source/drain regions connected between the multiplexer stage output and the first master pass gate node; (iv) a second master latch pass gate that includes a second n-channel master latch transistor having its gate connected to receive the clock signal and its source/drain regions connected between the first and second master pass gate nodes, and a second p-channel master latch transistor having its gate connected to receive the complement of the clock signal and its source/drain regions connected between the first and second master pass gate nodes; (v) a second master latch inverter having its input connected to the first master pass gate node and its output connected to the master latch stage output node; and (vi) a third master latch inverter having its input connected to the master latch stage output node and its output connected to the second master pass gate node. (c) a slave latch stage that includes a slave latch gating element connected to the master latch stage and responsive to the test enable control signal such that a data value stored in the master latch stage is provided from a master latch output node to the slave latch stage on periodic transitions of the clock signal when the test enable control signal is in the inactive logic state and is blocked from the slave latch stage when the test enable control signal is in the active logic state; and (d) a dynamic scan latch element that passes data value stored in the master latch stage to a scan data output of the scan flip-flop circuit on periodic transitions of the clock signal when the test enable control signal is in the active logic state.

Claim 7

A scan flip-flop circuit that holds state during scan shifting, the scan flip-flop circuit comprising: (a) a multiplexer stage that responds to a logic state of a test enable control signal by providing a normal data input signal received at a normal data input node as the multiplexer stage output when the test enable control signal is in an inactive logic state and by providing a scan data input signal received at a scan input node as the multiplexer stage output when the test enable control signal is in an active logic state, the multiplexer stage including: (i) a multiplexer inverter element that receives the test enable control signal and provides the complement of the test enable control signal at its output; (ii) a first multiplexer pass gate that includes a first n-channel multiplexer transistor having its gate connected to receive the test enable control signal and its source/drain regions connected between the normal data input node and the multiplexer stage output, and a first p-channel multiplexer transistor having its gate connected to receive the complement of the test enable control signal and its source/drain regions connected between the normal data input node and the multiplexer stage output; and (iii) a second multiplexer pass gate that includes a second n-channel multiplexer transistor having its gate connected to receive the complement of the test enable control signal and its source/drain regions connected between the scan data input node and the multiplexer stage output, and a second p-channel multiplexer transistor having its gate connected to receive the test enable control signal and its source/drain regions connected between the scan data input node and the multiplexer stage output; (b) a master latch stage connected to receive and store the multiplexer stage output on periodic transitions of a clock signal provided to the master latch stage; the master latch stage comprises: (i) a first master latch inverter connected to receive the clock signal and to provide the complement of the clock signal at its output; (ii) first and second master pass gate nodes; (iii) a first master latch pass gate that includes a first n-channel master latch transistor having its gate connected to receive the complement of the clock signal and its source/drain regions connected between the multiplexer stage output and the first master pass gate node, and a first p-channel master latch transistor having its gate connected to receive the clock signal and its source/drain regions connected between the multiplexer stage output and the first master pass gate node; (iv) a second master latch pass gate that includes a second n-channel master latch transistor having its gate connected to receive the clock signal and its source/drain regions connected between the first and second master pass gate nodes, and a second p-channel master latch transistor having its gate connected to receive the complement of the clock signal and its source/drain regions connected between the first and second master pass gate nodes; (v) a second master latch inverter having its input connected to the first master pass gate node and its output connected to the master latch stage output node; and (vi) a third master latch inverter having its input connected to the master latch stage output node and its output connected to the second master pass gate node. (c) a slave latch stage that includes a slave latch gating element connected to the master latch stage and responsive to the test enable control signal such that a data value stored in the master latch stage is provided from a master latch output node to the slave latch stage on periodic transitions of the clock signal when the test enable control signal is in the inactive logic state and is blocked from the slave latch stage when the test enable control signal is in the active logic state; and (d) a dynamic scan latch element that passes data value stored in the master latch stage to a scan data output of the scan flip-flop circuit on periodic transitions of the clock signal when the test enable control signal is in the active logic state.

Claim 8

A scan flip-flop circuit as in claim 4 and wherein the slave latch gating element comprises a gating element pass gate that includes a n-channel gating transistor having its gate connected to receive the test enable control signal and its source/drain regions connected between the master latch stage output node and a slave latch input node, and a p-channel gating transistor having its gate connected to receive the complement of the test enable control signal and its source/drain regions connected between the master latch output node stage and the slave latch input node.

Claim 9

A scan flip-flop circuit as in claim 5 and wherein the slave latch stage further comprises: first and second slave pass gate nodes; a data output node; a first slave latch pass gate that includes a first n-channel slave latch transistor having its gate connected to receive the clock signal and its source/drain regions connected between the slave stage input node and the first slave pass gate node, and a first p-channel slave latch transistor having its gate connected to receive the complement of the clock signal and its source/drain regions connected between the slave stage input node and the first slave pass gate node; a second slave latch pass gate that includes a second n-channel slave latch transistor having its gate connected to receive the complement of the clock signal and its source/drain regions connected between the first and second slave pass gate nodes, and a second p-channel slave latch transistor having its gate connected to receive the clock signal and its source/drain regions connected between the first and second slave pass gate nodes; a first slave latch inverter having its input connected to the first slave pass gate node and its output connected to the data output node to provide a normal data output signal; and a second slave latch inverter having its input connected to the data output node and its output connected to the second slave pass gate node such that the output of the second slave latch provides the complement of the normal data output signal.