US5633523A
Expired / Lapsed
US
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Complementary mis semiconductor device of dual gate structure having a silicide layer including a thinned portion
Assignee: Ricoh Co Ltd
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Filing: 1995-04-27
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Granted: 1997-05-27
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Expires: 2015-04-27
Abstract
Abstract In a complementary MIS semiconductor device of a dual gate structure, an N-type polysilicon layer for an N-channel transistor and a P-type polysilicon layer for a P-channel transistor are formed on a gate oxide film and a field oxide film. A recessed portion is formed on the field oxide film in a region including a junctioning region of the N-type polysilicon layer and the P-type polysilicon layer such that thicknesses of the polysilicon layers are reduced. A continuous silicide layer is formed on the polysilicon layers. The silicide layer is thin in the recessed portion on the field oxide film and is thick on an active region of each of the transistors. In this semiconductor device of a dual gate type, it is possible to prevent impurities of the polysilicon layers of gate electrodes from being diffused in a transversal direction and restrain an increase in resistance value of each of the gate electrodes.
Inventors
- 👤 Seiichi Kato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 05:22
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0172; H10D84/0174; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
136 words
A complementary MIS semiconductor device of a dual gate structure comprising: a P-channel MIS transistor having a gate electrode of a P-type polysilicon layer, the p-channel MIS transistor including an active region; an N-channel MIS transistor having a gate electrode of an N-type polysilicon layer, the N-channel MIS transistor including an active region; the polysilicon layers of both transistors being connected to each other directly or through an i-type polysilicon layer on a field oxide film for element separation; and a continuous silicide layer formed on at least a portion of the polysilicon layers of both transistors; and the complementary MIS semiconductor device being constructed such that a thickness of said silicide layer in a partial region on the field oxide film is thinner than that on the active region of each of the MIS transistors.
Claim 2
Dependent Claim
136 words
A complementary MIS semiconductor device of a dual gate structure comprising: a P-channel MIS transistor having a gate electrode of a P-type polysilicon layer, the p-channel MIS transistor including an active region; an N-channel MIS transistor having a gate electrode of an N-type polysilicon layer, the N-channel MIS transistor including an active region; the polysilicon layers of both transistors being connected to each other directly or through an i-type polysilicon layer on a field oxide film for element separation; and a continuous silicide layer formed on at least a portion of the polysilicon layers of both transistors; and the complementary MIS semiconductor device being constructed such that a thickness of said silicide layer in a partial region on the field oxide film is thinner than that on the active region of each of the MIS transistors.
Claim 3
Dependent Claim
48 words
A complementary MIS semiconductor device of a dual gate structure as claimed in claim 1, wherein a thickness of each of said polysilicon layers in said partial region providing the thin silicide layer is also thinner than that in the active region of each of the MIS transistors.
Claim 4
Dependent Claim
44 words
A complementary MIS semiconductor device of a dual gate structure as claimed in claim 1 or 2, wherein said partial region providing the thin silicide layer includes any one of a PN junction, a Pi junction and an iN junction of said polysilicon layers.
Claim 5
Dependent Claim
43 words
A complementary MIS semiconductor device of a dual gate structure as claimed in claim 1 or 2, wherein said partial region providing the thin silicide layer is located only in a P-type polysilicon region, an N-type polysilicon region or an i-type polysilicon region.
Claim 6
Dependent Claim
57 words
A complementary MIS semiconductor device of a dual gate structure as claimed in claim 1 or 2, wherein a thickness of the thin silicide region formed in said partial region is equal to or smaller than a size of one silicide grain with standard heat treatment over 600° C. in a manufacturing process of the MIS transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-26 | 2000-11-25 | 2001-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-26 | 2004-11-25 | 2005-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-26 | 2008-11-25 | 2009-05-27 | $7700.00 | Window Closed / Lapsed |