Patent US5631864A successfully refreshed from Google Patents.
US5631864A
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Memory array having a reduced number of metal source lines
Assignee: Micron Technology Inc
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Filing: 1995-07-28
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Granted: 1997-05-20
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Expires: 2015-07-28
Abstract
Abstract A flash memory array having a reduced number of metal source lines and increased storage density. The cells are arranged in rows and columns, with the cells in a row having their control gates connected to a common word line and the cells in a column having their drains connected to a common bit line. All of the cell sources of the array are connected together with a combination of doped semiconductor and metal lines. The source metal lines are disposed generally in parallel with the bit lines. In order to reduce the number of source metal lines, the lines are spaced apart by, typically, eight, sixteen or more cell columns. The metal source lines define a sub-array therebetween. The array includes a decoder for accessing two cells in different columns of each sub-array during single reading and programming operations. Thus, each sub-array provides two bits of data rather than the customary one bit. The reduced number of metal source lines saves a significant amount of die area with a only a small sacrifice in increased effective source line resistance.
Inventors
- 👤 Michael S. Briner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 10:24
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416
Claims Analysis
Total Claims: 39
Claim 1
Independent Claim
251 words
A memory array for use in a memory system comprising: an array of non-volatile memory cells, with each cell including a source, a drain, a channel region intermediate the source and drain, a floating gate disposed over the channel region and insulated from the channel region and a control gate disposed over the floating gate and insulated from the floating gate, with the cells being arranged in a plurality of rows and columns, with the cells located in one of the rows having their control gates connected to a common word line and with the cells located in a particular one of the columns having their drains connected to a common bit line and with all of the cells of the array having their sources connected to a common source connection, with the common source connection including a plurality of doped semiconductor source lines which connect the sources of the cells located in at least one of the rows together, and a metal source line structure including a plurality of metal source line column segments disposed generally parallel to the bit lines which connects together the doped source lines, with the metal source line column segments being spaced N number of cell columns apart so as to define a plurality of sub-arrays of the cells, with each sub-array having N number of columns; and decoder means for accessing at least two cells in one of the sub-arrays at the same time for the purpose of reading the at least two cells.
Claim 2
Dependent Claim
251 words
A memory array for use in a memory system comprising: an array of non-volatile memory cells, with each cell including a source, a drain, a channel region intermediate the source and drain, a floating gate disposed over the channel region and insulated from the channel region and a control gate disposed over the floating gate and insulated from the floating gate, with the cells being arranged in a plurality of rows and columns, with the cells located in one of the rows having their control gates connected to a common word line and with the cells located in a particular one of the columns having their drains connected to a common bit line and with all of the cells of the array having their sources connected to a common source connection, with the common source connection including a plurality of doped semiconductor source lines which connect the sources of the cells located in at least one of the rows together, and a metal source line structure including a plurality of metal source line column segments disposed generally parallel to the bit lines which connects together the doped source lines, with the metal source line column segments being spaced N number of cell columns apart so as to define a plurality of sub-arrays of the cells, with each sub-array having N number of columns; and decoder means for accessing at least two cells in one of the sub-arrays at the same time for the purpose of reading the at least two cells.
Claim 3
Dependent Claim
39 words
The memory array of claim 1 wherein the decoder means is also a means for accessing at least two cells in one of the sub-arrays at the same time for the purpose of programming the at least two cells.
Claim 4
Dependent Claim
51 words
The memory array of claim 2 wherein the decoder means includes a separate select transistor coupled to each of the bit lines of the array and means for generating select signals to turn on at least two of the select transistors associated with one of the sub-arrays at the same time.
Claim 5
Dependent Claim
34 words
The memory array of claim 3 wherein there are sixteen columns of cells in the sub-arrays and the cells accessed at the same time for reading and programming are spaced apart from each other.
Claim 6
Dependent Claim
31 words
The memory array of claim 3 wherein the cells accessed at the same time for reading and programming are located in separate columns of the sub-array N/2 number of columns apart.
Claim 7
Dependent Claim
34 words
The memory array of claim 5 wherein the metal source line structure includes a metal line disposed generally parallel to the word lines which connects adjacent ones of the metal source line column segments.
Claim 8
Dependent Claim
13 words
The memory array of claim 6 wherein the cells are flash memory cells.
Claim 9
Dependent Claim
200 words
A memory array for use in a memory system comprising: an array of flash memory cells arranged in a plurality of rows and a plurality of columns; a word line associated with each of the cell rows which connect control gates of the cells in associated rows together; a bit line associated with each of the cell columns which connect the drains of the cells all together in the associated column; an interconnection structure which interconnects the sources of the cells of the array together, the interconnection structure including doped semiconductor lines for connecting together at least some of the sources and including a metal line structure connected in parallel with the semiconductor lines, with the metal line structure including metal column segments generally disposed in parallel with the bit lines and spaced every N number of cell columns so as to define a sub-array of N number of cell columns intermediate adjacent ones of the metal column segments; and decoder means for accessing at least two cells at the same time in one of the sub-arrays during a single read operation, with the at least two cells being located in different ones of the cell columns of the sub-array.
Claim 10
Dependent Claim
200 words
A memory array for use in a memory system comprising: an array of flash memory cells arranged in a plurality of rows and a plurality of columns; a word line associated with each of the cell rows which connect control gates of the cells in associated rows together; a bit line associated with each of the cell columns which connect the drains of the cells all together in the associated column; an interconnection structure which interconnects the sources of the cells of the array together, the interconnection structure including doped semiconductor lines for connecting together at least some of the sources and including a metal line structure connected in parallel with the semiconductor lines, with the metal line structure including metal column segments generally disposed in parallel with the bit lines and spaced every N number of cell columns so as to define a sub-array of N number of cell columns intermediate adjacent ones of the metal column segments; and decoder means for accessing at least two cells at the same time in one of the sub-arrays during a single read operation, with the at least two cells being located in different ones of the cell columns of the sub-array.
Claim 11
Dependent Claim
26 words
The memory array of claim 8 wherein the decoder means is also a means for accessing the at least two cells in a single programming operation.
Claim 12
Dependent Claim
29 words
The memory array of claim 9 wherein there are sixteen number of cell columns in each of the cell sub-arrays and two cells are accessed in spaced apart columns.
Claim 13
Dependent Claim
199 words
A memory array for use in a memory system comprising: an array of flash memory cells arranged in a plurality of rows and a plurality of columns; a word line associated with each of the cell rows which connect control gates of the cells in associated rows together; a bit line associated with each of the cell columns which connect the sources of the cells all together in the associated columns; an interconnection structure which interconnects the drains of the cells of the array together, the interconnection structure including doped semiconductor lines for connecting together at least some of the drains and including a metal line structure connected in parallel with the semiconductor lines, with the metal line structure including metal column segments generally disposed in parallel with the bit lines and spaced every N number of cell columns so as to define a sub-array of N number of cell columns intermediate adjacent ones of the metal column segments; and decoder means for accessing at least two cells at the same time in one of the sub-arrays during a single read operation, with at least two cells being located in different ones of the cell columns of the sub-array.
Claim 14
Dependent Claim
199 words
A memory array for use in a memory system comprising: an array of flash memory cells arranged in a plurality of rows and a plurality of columns; a word line associated with each of the cell rows which connect control gates of the cells in associated rows together; a bit line associated with each of the cell columns which connect the sources of the cells all together in the associated columns; an interconnection structure which interconnects the drains of the cells of the array together, the interconnection structure including doped semiconductor lines for connecting together at least some of the drains and including a metal line structure connected in parallel with the semiconductor lines, with the metal line structure including metal column segments generally disposed in parallel with the bit lines and spaced every N number of cell columns so as to define a sub-array of N number of cell columns intermediate adjacent ones of the metal column segments; and decoder means for accessing at least two cells at the same time in one of the sub-arrays during a single read operation, with at least two cells being located in different ones of the cell columns of the sub-array.
Claim 15
Dependent Claim
25 words
The memory array of claim 11 wherein the decoder means is also a means for accessing at least two cells in a single programming operation.
Claim 16
Dependent Claim
29 words
The memory array of claim 12 wherein there are sixteen number of cell columns in each of the cell sub-arrays and two cells are accessed in spaced apart columns.
Claim 17
Dependent Claim
225 words
A memory array for use in a memory system comprising: an array of memory cells, with each cell including a source, a drain, a channel region intermediate the source and drain, and a gate disposed over the channel region with the cells being arranged in a plurality of rows and columns, with the cells located in one of the rows having their gates connected to a common word line and with the cells located in a particular one of the columns having their drains connected to a common bit line and with all of the cells of the array having their sources connected to a common source connection, with the common source connection including a plurality of doped semiconductor source lines which connect the sources of the cells located in one of the rows together, and a metal source line structure including a plurality of metal source line column segments disposed generally parallel to the bit lines which connects together the doped source lines, with the metal source line column segments being spaced N number of cell columns apart so as to define a plurality of sub-arrays of the cells, with each sub-array having N number of columns; and decoder means for accessing at least two cells in one of the sub-arrays at the same time for the purpose of reading at least two cells.
Claim 18
Dependent Claim
225 words
A memory array for use in a memory system comprising: an array of memory cells, with each cell including a source, a drain, a channel region intermediate the source and drain, and a gate disposed over the channel region with the cells being arranged in a plurality of rows and columns, with the cells located in one of the rows having their gates connected to a common word line and with the cells located in a particular one of the columns having their drains connected to a common bit line and with all of the cells of the array having their sources connected to a common source connection, with the common source connection including a plurality of doped semiconductor source lines which connect the sources of the cells located in one of the rows together, and a metal source line structure including a plurality of metal source line column segments disposed generally parallel to the bit lines which connects together the doped source lines, with the metal source line column segments being spaced N number of cell columns apart so as to define a plurality of sub-arrays of the cells, with each sub-array having N number of columns; and decoder means for accessing at least two cells in one of the sub-arrays at the same time for the purpose of reading at least two cells.
Claim 19
Dependent Claim
51 words
The memory array of claim 14 wherein the decoder means includes a separate select transistor coupled to each of the bit lines of the array and means for generating select signals to turn on at least two of the select transistors associated with one of the sub-arrays at the same time.
Claim 20
Dependent Claim
32 words
The memory array of claim 15 wherein there are sixteen columns of cells in the sub-arrays and the cells accessed at the same time for reading are spaced apart from each other.
Claim 21
Dependent Claim
29 words
The memory array of claim 15 wherein the cells accessed at the same time for reading are located in separate columns of the sub-array N/2 number of columns apart.
Claim 22
Dependent Claim
33 words
The memory of claim 17 wherein the metal source line structure includes a metal line disposed generally parallel to the word lines which connects adjacent ones of the metal source line column segments.
Claim 23
Dependent Claim
202 words
A memory array for use in a memory system comprising: an array of memory cells with the cells being arranged in a plurality of rows and columns, with the cells located in one of the rows being connected to a common word line, and with the cells located in a particular one of the columns being selectively connected to a common bit line by the word line and with all of the cells of the array having a common V SS connection; wherein the common V SS connection includes a plurality of doped semiconductor V SS connections which connect the cells located in at least one of the rows together, and includes a metal V SS line structure including a plurality of metal line column segments disposed generally parallel to the bit lines which connects together the V SS connections, with the metal V SS line column segments being spaced N number of cell columns apart so as to define a plurality of sub-arrays of the cells, with each sub-array having N number of columns; and decoder means for accessing at least two cells in one of the sub-arrays at the same time for the purpose of reading at least two cells.
Claim 24
Dependent Claim
202 words
A memory array for use in a memory system comprising: an array of memory cells with the cells being arranged in a plurality of rows and columns, with the cells located in one of the rows being connected to a common word line, and with the cells located in a particular one of the columns being selectively connected to a common bit line by the word line and with all of the cells of the array having a common V SS connection; wherein the common V SS connection includes a plurality of doped semiconductor V SS connections which connect the cells located in at least one of the rows together, and includes a metal V SS line structure including a plurality of metal line column segments disposed generally parallel to the bit lines which connects together the V SS connections, with the metal V SS line column segments being spaced N number of cell columns apart so as to define a plurality of sub-arrays of the cells, with each sub-array having N number of columns; and decoder means for accessing at least two cells in one of the sub-arrays at the same time for the purpose of reading at least two cells.
Claim 25
Dependent Claim
29 words
The memory array of claim 19 wherein the decoder means is also a means for writing at least two cells in one of the sub-arrays at the same time.
Claim 26
Dependent Claim
51 words
The memory array of claim 20 wherein the decoder means includes a separate select transistor coupled to each of the bit lines of the array and means for generating select signals to turn on at least two of the select transistors associated with one of the sub-arrays at the same time.
Claim 27
Dependent Claim
34 words
The memory array of claim 21 wherein there are sixteen columns of cells in the sub-arrays and the cells accessed at the same time for reading and writing are spaced apart from each other.
Claim 28
Dependent Claim
31 words
The memory array of claim 21 wherein the cells accessed at the same time for reading and writing are located in separate columns of the sub-array N/2 number of columns apart.
Claim 29
Dependent Claim
33 words
The memory of claim 22 wherein the metal source line structure includes a metal line disposed generally parallel to the word lines which connects adjacent ones of the metal source line column segments.
Claim 30
Dependent Claim
251 words
A memory array for use in a memory system comprising: an array of non-volatile memory cells, with each cell including a source, a drain, a channel region intermediate the source and drain, a floating gate disposed over the channel region and insulated from the channel region and a control gate disposed over the floating gate and insulated from the floating gate, with the cells being arranged in a plurality of rows and columns, with the cells located in one of the rows having their control gates connected to a common word line and with the cells located in a particular one of the columns having their drains connected to a common bit line and with all of the cells of the array having their sources connected to a common source connection, with the common source connection including a plurality of doped semiconductor source lines which connect the sources of the cells located in at least one of the rows together, and a metal source line structure including a plurality of metal source line column segments disposed generally parallel to the bit lines which connects together the doped source lines, with the metal source line column segments being spaced N number of cell columns apart so as to define a plurality of sub-arrays of the cells, with each sub-array having N number of columns; and a decoder which accesses at least two cells in one of the sub-arrays at the same time for the purpose of reading the at least two cells.
Claim 31
Dependent Claim
251 words
A memory array for use in a memory system comprising: an array of non-volatile memory cells, with each cell including a source, a drain, a channel region intermediate the source and drain, a floating gate disposed over the channel region and insulated from the channel region and a control gate disposed over the floating gate and insulated from the floating gate, with the cells being arranged in a plurality of rows and columns, with the cells located in one of the rows having their control gates connected to a common word line and with the cells located in a particular one of the columns having their drains connected to a common bit line and with all of the cells of the array having their sources connected to a common source connection, with the common source connection including a plurality of doped semiconductor source lines which connect the sources of the cells located in at least one of the rows together, and a metal source line structure including a plurality of metal source line column segments disposed generally parallel to the bit lines which connects together the doped source lines, with the metal source line column segments being spaced N number of cell columns apart so as to define a plurality of sub-arrays of the cells, with each sub-array having N number of columns; and a decoder which accesses at least two cells in one of the sub-arrays at the same time for the purpose of reading the at least two cells.
Claim 32
Dependent Claim
200 words
A memory array for use in a memory system comprising: an array of flash memory cells arranged in a plurality of rows and a plurality of columns; a word line associated with each of the cell rows which connect control gates of the cells in associated rows together; a bit line associated with each of the cell columns which connect the drains of the cells all together in the associated column; an interconnection structure which interconnects the sources of the cells of the array together, the interconnection structure including doped semiconductor lines for connecting together at least some of the sources and including a metal line structure connected in parallel with the semiconductor lines, with the metal line structure including metal column segments generally disposed in parallel with the bit lines and spaced every N number of cell columns so as to define a sub-array of N number of cell columns intermediate adjacent ones of the metal column segments; and a decoder which accesses at least two cells at the same time in one of the sub-arrays during a single read operation, with the at least two cells being located in different ones of the cell columns of the sub-array.
Claim 33
Dependent Claim
200 words
A memory array for use in a memory system comprising: an array of flash memory cells arranged in a plurality of rows and a plurality of columns; a word line associated with each of the cell rows which connect control gates of the cells in associated rows together; a bit line associated with each of the cell columns which connect the drains of the cells all together in the associated column; an interconnection structure which interconnects the sources of the cells of the array together, the interconnection structure including doped semiconductor lines for connecting together at least some of the sources and including a metal line structure connected in parallel with the semiconductor lines, with the metal line structure including metal column segments generally disposed in parallel with the bit lines and spaced every N number of cell columns so as to define a sub-array of N number of cell columns intermediate adjacent ones of the metal column segments; and a decoder which accesses at least two cells at the same time in one of the sub-arrays during a single read operation, with the at least two cells being located in different ones of the cell columns of the sub-array.
Claim 34
Dependent Claim
199 words
A memory array for use in a memory system comprising: an array of flash memory cells arranged in a plurality of rows and a plurality of columns; a word line associated with each of the cell rows which connect control gates of the cells in associated rows together; a bit line associated with each of the cell columns which connect the sources of the cells all together in the associated columns; an interconnection structure which interconnects the drains of the cells of the array together, the interconnection structure including doped semiconductor lines for connecting together at least some of the drains and including a metal line structure connected in parallel with the semiconductor lines, with the metal line structure including metal column segments generally disposed in parallel with the bit lines and spaced every N number of cell columns so as to define a sub-array of N number of cell columns intermediate adjacent ones of the metal column segments; and a decoder which accesses at least two cells at the same time in one of the sub-arrays during a single read operation, with at least two cells being located in different ones of the cell columns of the sub-array.
Claim 35
Dependent Claim
199 words
A memory array for use in a memory system comprising: an array of flash memory cells arranged in a plurality of rows and a plurality of columns; a word line associated with each of the cell rows which connect control gates of the cells in associated rows together; a bit line associated with each of the cell columns which connect the sources of the cells all together in the associated columns; an interconnection structure which interconnects the drains of the cells of the array together, the interconnection structure including doped semiconductor lines for connecting together at least some of the drains and including a metal line structure connected in parallel with the semiconductor lines, with the metal line structure including metal column segments generally disposed in parallel with the bit lines and spaced every N number of cell columns so as to define a sub-array of N number of cell columns intermediate adjacent ones of the metal column segments; and a decoder which accesses at least two cells at the same time in one of the sub-arrays during a single read operation, with at least two cells being located in different ones of the cell columns of the sub-array.
Claim 36
Dependent Claim
225 words
A memory array for use in a memory system comprising: an array of memory cells, with each cell including a source, a drain, a channel region intermediate the source and drain, and a gate disposed over the channel region with the cells being arranged in a plurality of rows and columns, with the cells located in one of the rows having their gates connected to a common word line and with the cells located in a particular one of the columns having their drains connected to a common bit line and with all of the cells of the array having their sources connected to a common source connection, with the common source connection including a plurality of doped semiconductor source lines which connect the sources of the cells located in one of the rows together, and a metal source line structure including a plurality of metal source line column segments disposed generally parallel to the bit lines which connects together the doped source lines, with the metal source line column segments being spaced N number of cell columns apart so as to define a plurality of sub-arrays of the cells, with each sub-array having N number of columns; and a decoder which accesses at least two cells in one of the sub-arrays at the same time for the purpose of reading at least two cells.
Claim 37
Dependent Claim
225 words
A memory array for use in a memory system comprising: an array of memory cells, with each cell including a source, a drain, a channel region intermediate the source and drain, and a gate disposed over the channel region with the cells being arranged in a plurality of rows and columns, with the cells located in one of the rows having their gates connected to a common word line and with the cells located in a particular one of the columns having their drains connected to a common bit line and with all of the cells of the array having their sources connected to a common source connection, with the common source connection including a plurality of doped semiconductor source lines which connect the sources of the cells located in one of the rows together, and a metal source line structure including a plurality of metal source line column segments disposed generally parallel to the bit lines which connects together the doped source lines, with the metal source line column segments being spaced N number of cell columns apart so as to define a plurality of sub-arrays of the cells, with each sub-array having N number of columns; and a decoder which accesses at least two cells in one of the sub-arrays at the same time for the purpose of reading at least two cells.
Claim 38
Dependent Claim
200 words
A memory array for use in a memory system comprising: an array of memory cells with the cells being arranged in a plurality of rows and columns, with the cells located in one of the rows being connected to a common word line, and with the cells located in a particular one of the columns being selectively connected to a common bit line by the word line and with all of the cells of the array having a common V SS connection; wherein the common V SS connection includes a plurality of doped semiconductor V SS connections which connect the cells located in at least one of the rows together, and includes a metal V SS line structure including a plurality of metal line column segments disposed generally parallel to lines which connects together the V SS connections, with the metal V SS line column segments being spaced N number of cell columns apart so as to define a plurality of sub-arrays of the cells, with each sub-array having N number of columns; and a decoder which accesses at least two cells in one of the sub-arrays at the same time for the purpose of reading at least two cells.
Claim 39
Dependent Claim
200 words
A memory array for use in a memory system comprising: an array of memory cells with the cells being arranged in a plurality of rows and columns, with the cells located in one of the rows being connected to a common word line, and with the cells located in a particular one of the columns being selectively connected to a common bit line by the word line and with all of the cells of the array having a common V SS connection; wherein the common V SS connection includes a plurality of doped semiconductor V SS connections which connect the cells located in at least one of the rows together, and includes a metal V SS line structure including a plurality of metal line column segments disposed generally parallel to lines which connects together the V SS connections, with the metal V SS line column segments being spaced N number of cell columns apart so as to define a plurality of sub-arrays of the cells, with each sub-array having N number of columns; and a decoder which accesses at least two cells in one of the sub-arrays at the same time for the purpose of reading at least two cells.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-19 | 2000-11-18 | 2001-05-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-19 | 2004-11-18 | 2005-05-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-19 | 2008-11-18 | 2009-05-20 | $7700.00 | Window Closed / Lapsed |