US5631648A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signal compression or expansion circuit for mobile communication
Assignee: Sony Corp
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Filing: 1994-12-12
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Granted: 1997-05-20
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Expires: 2014-12-12
Abstract
Abstract A signal-processing circuit adapted for signal compression and expansion performed in the transmitter and receiver of mobile communication equipment. The signal-processing circuit comprises a multiplication type D/A converter to which an analog signal is applied, a level detector circuit that detects the level of the analog signal, and an A/D converter. The D/A converter converts the analog input signal into an analog output signal having an amplitude corresponding to digital control data. The A/D converter digitizes the output signal from the level detector circuit and supplies it as said digital control data to the D/A converter. These circuits can be fabricated from CMOS circuits.
Inventors
- 👤 Takaaki Yamada
- 👤 Kazuo Kumano
- 👤 Kazuhiro Takeda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 09:56
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/62; H04B1/64
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
177 words
A signal-processing circuit formed by CMOS processes, comprising: a logarithmically linear scale multiplication type CMOS digital-to-analog converter having a resistor bank which converts an audio range analog input signal applied to the converter into an analog output signal having an amplitude corresponding to digital control data; a level detector means for detecting the level of audio range, said level means having a full wave rectifier and an attack and recovery circuit; and a logarithmically linear scale analog-to-digital converter which digitizes the output signal from the level detector means and supplies the digitized signal as the above-described digital control data to the multiplication type digital-to-analog converter such that a level of an output signal is a square of a level of said analog signal applied to said converter, said analog-to-digital converter being a successive approximation type converter having a plurality of resistors and switches connected to perform an analog to digital conversion, said switches including switches connected between said resistors and switches connected at intermediate points along said resistors to provide fine or coarse adjustments of the steps.
Claim 2
Dependent Claim
177 words
A signal-processing circuit formed by CMOS processes, comprising: a logarithmically linear scale multiplication type CMOS digital-to-analog converter having a resistor bank which converts an audio range analog input signal applied to the converter into an analog output signal having an amplitude corresponding to digital control data; a level detector means for detecting the level of audio range, said level means having a full wave rectifier and an attack and recovery circuit; and a logarithmically linear scale analog-to-digital converter which digitizes the output signal from the level detector means and supplies the digitized signal as the above-described digital control data to the multiplication type digital-to-analog converter such that a level of an output signal is a square of a level of said analog signal applied to said converter, said analog-to-digital converter being a successive approximation type converter having a plurality of resistors and switches connected to perform an analog to digital conversion, said switches including switches connected between said resistors and switches connected at intermediate points along said resistors to provide fine or coarse adjustments of the steps.
Claim 3
Dependent Claim
24 words
The signal-processing circuit of claim 1, further comprising an offset-correcting circuit which corrects the offset of the output signal from the level detector circuit.
Claim 4
Dependent Claim
60 words
The signal-processing circuit of claim 2, further comprising a control means which, when the input to the level detector circuit is absent, monitors said digital control data while changing the corrected control input to the offset-correcting circuit in a stepwise fashion and which, when the digital control data assume the least values, stops the correction made by the offset-correcting circuit.
Claim 5
Dependent Claim
49 words
The signal-processing circuit of claim 1, further comprising: a negative feedback circuit including an operational amplifier having an inverting input to which the analog input signal is applied, and wherein the output from the operational amplifier is used as said analog output signal and applied to the signal-processing circuit.
Claim 6
Dependent Claim
181 words
A signal expansion or compression circuit formed by CMOS processes, comprising: a logarithmically linear scale multiplication type CMOS digital-to-analog converter having a resistor bank of resistors and a plurality Of switches connected to said resistor bank with ones of said switches connected between said resisters and others of said switches connected along said resistors to provide rough and fine levels and having an input for receiving an audio range analog signal and having a digital converter which converts an analog signal applied to the converter into an analog output signal having an amplitude corresponding to digital control data; a level detector circuit that detects the level of the audio range analog input signal, said level detector circuit including a full wave rectifier and an attack and recovery circuit; and an analog-to-digital converter which digitizes the output signal from the level detector circuit and supplies the digitized signal as the above-described digital control data to the multiplication type digital-to-analog converter such that a level of an output signal is a square of a level of said analog signal applied to said converter.
Claim 7
Dependent Claim
181 words
A signal expansion or compression circuit formed by CMOS processes, comprising: a logarithmically linear scale multiplication type CMOS digital-to-analog converter having a resistor bank of resistors and a plurality Of switches connected to said resistor bank with ones of said switches connected between said resisters and others of said switches connected along said resistors to provide rough and fine levels and having an input for receiving an audio range analog signal and having a digital converter which converts an analog signal applied to the converter into an analog output signal having an amplitude corresponding to digital control data; a level detector circuit that detects the level of the audio range analog input signal, said level detector circuit including a full wave rectifier and an attack and recovery circuit; and an analog-to-digital converter which digitizes the output signal from the level detector circuit and supplies the digitized signal as the above-described digital control data to the multiplication type digital-to-analog converter such that a level of an output signal is a square of a level of said analog signal applied to said converter.
Claim 8
Dependent Claim
67 words
A signal-processing circuit as claimed in claim 1, wherein said resistor bank comprises a plurality of first resistors connected to one another at junctions and a plurality of parallel connected second resistors connected to junctions of said first resistors, said digital-to-analog converter including a plurality of switches connected to said junctions of said first resistors, and a switch control circuit connected to operate said plurality of switches.
Claim 9
Dependent Claim
22 words
A signal-processing circuit as claimed in claim 1, wherein said signal-processing circuit is formed on a single circuit chip using CMOS techniques.
Claim 10
Dependent Claim
70 words
A signal expansion or compression circuit as claimed in claim 5, wherein said resistor bank comprises a plurality of first resistors connected to one another at junctions and a plurality of parallel connected second resistors connected to junctions of said first resistors, said digital-to-analog converter including a plurality of switches connected to said junctions of said first resistors, and a switch control circuit connected to operate said plurality of switches.
Claim 11
Dependent Claim
28 words
A signal expansion or compression circuit as claimed in claim 5, wherein said signal expansion or compression circuit is formed on a single circuit chip using CMOS techniques.
References Cited (Backward Citations)
US2889409A
Cited
US3684968A
Cited
US4020485A
Cited
US3882484A
Cited
US4062013A
Cited
US4875049A
Cited
US4851842A
Cited
JPS6471309A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-19 | 2000-11-18 | 2001-05-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-19 | 2004-11-18 | 2005-05-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-19 | 2008-11-18 | 2009-05-20 | $7700.00 | Window Closed / Lapsed |