US5630100A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Simulating multi-phase clock designs using a single clock edge based system
Assignee: Advanced Micro Devices Inc
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Filing: 1994-10-17
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Granted: 1997-05-13
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Expires: 2014-10-17
Abstract
Abstract A method for converting a multiple-phase circuit to single-clock-edge circuit includes the steps of receiving a data signal at an input terminal, receiving a system clock signal having a system clock frequency and receiving a phase clock signal having a frequency divided from the system clock frequency. The data signal is transferred to an output terminal when the phase clock signal is active and latched upon the occurrence of an edge transition of the system clock signal when the phase clock signal is active. When the phase clock signal is inactive, the latched data signal is latched again upon the occurrence of the edge transition of the system clock signal. The latched data signal is transferred to the output terminal when the phase clock signal is inactive.
Inventors
- 👤 Gopi Ganapathy
- 👤 David B. Witt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 14:49
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/44; G06F9/455; G06F5/00; G06F5/06; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318552; G06F11/00; G06F11/22; G06F11/26; G06F11/261; G06F30/00; G06F30/30; G06F30/32; G06F30/33; H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
152 words
A simulator circuit for simulating a multiple-phase circuit using a single-clock-edge system comprising: a data node; a system clock node; a phase generator having an input terminal coupled to the system clock node and an output terminal; a first control switch having a first input terminal coupled to the data node, a second input terminal, a control terminal coupled to the output terminal of the phase generator and an output terminal; a latch having an input terminal coupled to the first control switch output terminal, an output terminal coupled to the first input terminal of the first control switch and a clock terminal coupled to the system clock node; and a second control switch having a first input terminal coupled to the data node, a second input terminal coupled to the output terminal of the latch, a control terminal coupled to the output terminal of the phase generator and an output terminal.
Claim 2
Dependent Claim
152 words
A simulator circuit for simulating a multiple-phase circuit using a single-clock-edge system comprising: a data node; a system clock node; a phase generator having an input terminal coupled to the system clock node and an output terminal; a first control switch having a first input terminal coupled to the data node, a second input terminal, a control terminal coupled to the output terminal of the phase generator and an output terminal; a latch having an input terminal coupled to the first control switch output terminal, an output terminal coupled to the first input terminal of the first control switch and a clock terminal coupled to the system clock node; and a second control switch having a first input terminal coupled to the data node, a second input terminal coupled to the output terminal of the latch, a control terminal coupled to the output terminal of the phase generator and an output terminal.
Claim 3
Dependent Claim
55 words
A circuit as in claim 1 further comprising: a condition signal node; an AND gate having a first input terminal coupled to the output terminal of the phase generator, a second input terminal coupled to the condition signal node and an output terminal coupled to the control terminals of the first and second control switches.
Claim 4
Dependent Claim
15 words
A circuit according to claim 1 wherein the first and second control switches are multiplexers.
Claim 5
Dependent Claim
13 words
A circuit according to claim 1 wherein the latch is a D flip-flop.
Claim 6
Dependent Claim
124 words
A sequential logic circuit comprising: a data node; a system clock node; a phase generator having an input terminal coupled to the system clock node and an output terminal; a first multiple-phase latch mapping circuit having a data input terminal coupled to the data node, an enable terminal coupled to the output terminal of the phase generator and an output terminal; a combinational logic block having an input terminal coupled to the output terminal of the first multiple-phase latch mapping circuit and having an output terminal; and a second multiple-phase latch mapping circuit having a data input terminal coupled to the output terminal of the combinational logic block, an enable terminal coupled to the output terminal of the phase generator and an output terminal.
Claim 7
Dependent Claim
124 words
A sequential logic circuit comprising: a data node; a system clock node; a phase generator having an input terminal coupled to the system clock node and an output terminal; a first multiple-phase latch mapping circuit having a data input terminal coupled to the data node, an enable terminal coupled to the output terminal of the phase generator and an output terminal; a combinational logic block having an input terminal coupled to the output terminal of the first multiple-phase latch mapping circuit and having an output terminal; and a second multiple-phase latch mapping circuit having a data input terminal coupled to the output terminal of the combinational logic block, an enable terminal coupled to the output terminal of the phase generator and an output terminal.
Claim 8
Dependent Claim
129 words
A circuit as in claim 5 wherein the first multiple-phase latch mapping circuit comprises: a first control switch having a first input terminal coupled to the data node, a second input terminal, a control terminal coupled to the output terminal of the phase generator and an output terminal; a latch having an input terminal coupled to the first control switch output terminal, an output terminal coupled to the first input terminal of the first control switch and a clock terminal coupled to the system clock node; and a second control switch having a first input terminal coupled to the data node, a second input terminal coupled to the output terminal of the latch, a control terminal coupled to the output terminal of the phase generator and an output terminal.
Claim 9
Dependent Claim
15 words
A circuit according to claim 6 wherein the first and second control switches are multiplexers.
Claim 10
Dependent Claim
13 words
A circuit according to claim 6 wherein the latch is a D flip-flop.
Claim 11
Dependent Claim
55 words
A circuit as in claim 5 further comprising: a condition signal node; an AND gate having a first input terminal coupled to the output terminal of the phase generator, a second input terminal coupled to the condition signal node and an output terminal coupled to the control terminals of the first and second control switches.
Claim 12
Independent Claim
143 words
An apparatus for converting a multiple-phase circuit to a single-clock-edge circuit comprising: a first control switch having a first input terminal coupled to a data node, a second input terminal, a control terminal coupled to receive a phase clock signal having a phase clock frequency and an output terminal; a latch having an input terminal coupled to the first control switch output terminal, an output terminal coupled to the first input terminal of the first control switch and a clock terminal coupled to receive a system clock signal having a system clock frequency which is a multiple of the phase clock frequency; and a second control switch having a first input terminal coupled to the data node, a second input terminal coupled to the output terminal of the latch, a control terminal coupled to receive the phase clock signal and an output terminal.
Claim 13
Independent Claim
143 words
An apparatus for converting a multiple-phase circuit to a single-clock-edge circuit comprising: a first control switch having a first input terminal coupled to a data node, a second input terminal, a control terminal coupled to receive a phase clock signal having a phase clock frequency and an output terminal; a latch having an input terminal coupled to the first control switch output terminal, an output terminal coupled to the first input terminal of the first control switch and a clock terminal coupled to receive a system clock signal having a system clock frequency which is a multiple of the phase clock frequency; and a second control switch having a first input terminal coupled to the data node, a second input terminal coupled to the output terminal of the latch, a control terminal coupled to receive the phase clock signal and an output terminal.
Claim 14
Dependent Claim
62 words
An apparatus according to claim 10 wherein the first control switch passes a signal from the first control switch first input terminal to the first control switch output terminal when the phase clock signal is active and passes a signal from the first control switch second input terminal to the first control switch output terminal when the phase clock signal is inactive.
Claim 15
Dependent Claim
61 words
An apparatus according to claim 11 wherein the second control switch passes a signal from the second control switch first input terminal to the second control switch output terminal when the phase clock signal is active and passes a signal from the second control switch second input terminal to the second control switch output terminal when the phase clock is inactive.
Claim 16
Dependent Claim
61 words
An apparatus according to claim 10 wherein the second control switch passes a signal from the second control switch first input terminal to the second control switch output terminal when the phase clock signal is active and passes a signal from the second control switch second input terminal to the second control switch output terminal when the phase clock is inactive.
Claim 17
Dependent Claim
23 words
An apparatus according to claim 10 wherein the latch latches data on the input terminal on an edge of the system clock signal.
Claim 18
Dependent Claim
24 words
An apparatus according to claim 10 wherein the apparatus is an emulated circuit for emulating a multiple-phase circuit using a single-clock-edge triggered test system.
Claim 19
Dependent Claim
27 words
An apparatus according to claim 15 wherein the single-clock-edge triggered test system is a system selected from the group of circuit emulators, simulators, cycle-based simulators, event-driven simulators.
Claim 20
Dependent Claim
15 words
An apparatus according to claim 10 wherein the first and second control switches are multiplexers.
Claim 21
Dependent Claim
13 words
An apparatus according to claim 10 wherein the latch is a D flip-flop.
Claim 22
Dependent Claim
72 words
An apparatus according to claim 10 wherein the phase clock signal is a conditional signal and the apparatus further comprises: an AND gate having a first input terminal coupled to receive a condition signal, a second input terminal coupled to receive an unconditional phase clock signal and an output terminal coupled to the first control switch control terminal and the second control switch control terminal to supply the conditional phase clock signal.
Claim 23
Independent Claim
123 words
An apparatus for converting a multiple-phase circuit to a single-clock-edge circuit comprising: an input multiplexer controlled by a phase clock signal having a phase clock frequency for selecting an input signal between a data signal and a feedback signal; a flip-flop coupled to the input multiplexer to receive the input signal and controlled by a system clock signal having a system clock frequency which is a multiple of the phase clock frequency for latching the input signal on a clock edge of the system clock signal; and an output multiplexer controlled by the phase clock signal for selecting an output signal between the data signal and the latched signal, the latched signal being fed back to the input multiplexer as the feedback signal.
Claim 24
Independent Claim
123 words
An apparatus for converting a multiple-phase circuit to a single-clock-edge circuit comprising: an input multiplexer controlled by a phase clock signal having a phase clock frequency for selecting an input signal between a data signal and a feedback signal; a flip-flop coupled to the input multiplexer to receive the input signal and controlled by a system clock signal having a system clock frequency which is a multiple of the phase clock frequency for latching the input signal on a clock edge of the system clock signal; and an output multiplexer controlled by the phase clock signal for selecting an output signal between the data signal and the latched signal, the latched signal being fed back to the input multiplexer as the feedback signal.
Claim 25
Dependent Claim
46 words
An apparatus according to claim 20 wherein the phase clock signal is a conditional signal further comprising: an AND gate for ANDing a condition signal with an unconditional phase clock signal supplying the conditional phase clock signal result to the input multiplexer and the output multiplexer.
Claim 26
Dependent Claim
36 words
An apparatus according to claim 20 wherein the apparatus is an emulated circuit for emulating a multiple-phase circuit in a single-clock-edge triggered test system selected from the group of circuit emulators, simulators, cycle-based simulators, event-driven simulators.
Claim 27
Independent Claim
181 words
A system for converting the operation of a multiple-phase, level-sensitive transparent device to an edge-sensitive operation comprising: an input switch having a first input terminal coupled to the multiple-phase, level-sensitive transparent device for receiving an operating signal, having a second input terminal for receiving a feedback signal, having a control terminal for receiving a phase signal of a multiple-phase timing signal, and having an output terminal; an edge-sensitive trigger device having an input terminal coupled to the output terminal of the input switch, having a control terminal coupled to receive a system clock signal, and having an output terminal coupled to the second input terminal of the input switch for supplying a feedback signal; and an output switch having a first input terminal coupled to the multiple-phase, level-sensitive transparent device for receiving an operating signal, having a second input terminal coupled to the output terminal of the edge-sensitive trigger device, having a control terminal for receiving the phase signal of the multiple-phase timing signal, and having an output terminal for generating an edge-sensitive output signal synchronous with the system clock signal.
Claim 28
Independent Claim
181 words
A system for converting the operation of a multiple-phase, level-sensitive transparent device to an edge-sensitive operation comprising: an input switch having a first input terminal coupled to the multiple-phase, level-sensitive transparent device for receiving an operating signal, having a second input terminal for receiving a feedback signal, having a control terminal for receiving a phase signal of a multiple-phase timing signal, and having an output terminal; an edge-sensitive trigger device having an input terminal coupled to the output terminal of the input switch, having a control terminal coupled to receive a system clock signal, and having an output terminal coupled to the second input terminal of the input switch for supplying a feedback signal; and an output switch having a first input terminal coupled to the multiple-phase, level-sensitive transparent device for receiving an operating signal, having a second input terminal coupled to the output terminal of the edge-sensitive trigger device, having a control terminal for receiving the phase signal of the multiple-phase timing signal, and having an output terminal for generating an edge-sensitive output signal synchronous with the system clock signal.
Claim 29
Dependent Claim
14 words
A system according to claim 23 wherein the input and output switches are multiplexers.
Claim 30
Dependent Claim
14 words
A system according to claim 23 wherein the edge-sensitive trigger device is a latch.
Claim 31
Dependent Claim
15 words
A system according to claim 23 wherein the edge-sensitive trigger device is a D flip-flop.
Claim 32
Dependent Claim
59 words
A system according to claim 23 wherein the input switch passes the operating signal from the input switch first input terminal to the input switch output terminal when the phase clock signal is active and passes the feedback signal from the input switch second input terminal to the input switch output terminal when the phase clock signal is inactive.
Claim 33
Dependent Claim
61 words
A system according to claim 27 wherein the output switch passes the operating signal from the output switch first input terminal to the output switch output terminal when the phase clock signal is active and passes the edge-sensitive trigger device output signal from the output switch second input terminal to the output switch output terminal when the phase clock is inactive.
Claim 34
Dependent Claim
61 words
A system according to claim 23 wherein the output switch passes the operating signal from the output switch first input terminal to the output switch output terminal when the phase clock signal is active and passes the edge-sensitive trigger device output signal from the output switch second input terminal to the output switch output terminal when the phase clock is inactive.
Claim 35
Dependent Claim
25 words
A system according to claim 23 wherein the edge-sensitive trigger device latches data on the input terminal on an edge of the system clock signal.
Claim 36
Dependent Claim
24 words
A system according to claim 23 wherein the system is an emulated circuit for emulating a multiple-phase circuit using a single-clock-edge triggered test system.
Claim 37
Dependent Claim
27 words
A system according to claim 31 wherein the single-clock-edge triggered test system is a system selected from the group of circuit emulators, simulators, cycle-based simulators, event-driven simulators.
Claim 38
Dependent Claim
69 words
A system according to claim 31 wherein the phase signal is a conditional signal and the system further comprises: an AND gate having a first input terminal coupled to receive a condition signal, a second input terminal coupled to receive an unconditional phase clock signal and an output terminal coupled to the input switch control terminal and the output switch control terminal to supply the conditional phase clock signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-12 | 2000-11-11 | 2001-05-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-12 | 2004-11-11 | 2005-05-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-12 | 2008-11-11 | 2009-05-13 | $7700.00 | Window Closed / Lapsed |