US5629950A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fault management scheme for a cache memory
Assignee: Hewlett Packard Development Co LP
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Filing: 1996-07-08
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Granted: 1997-05-13
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Expires: 2016-07-08
Abstract
Abstract The present invention is directed to a method of managing a cache upon detection of an address TAG parity error, The cache includes a plurality of entries for storage of data, with each entry having a corresponding address TAG entry. The method includes the steps of performing a TAG parity check for each access to the cache, and upon detection of a parity error in an address TAG, disabling allocation of TAG entries for storage of new address TAGs. A signal indicating the TAG parity error is transmitted to an error correction mechanism.
Inventors
- 👤 Nitin D. Godiwala
- 👤 Kurt M. Thaller
- 👤 Jeffrey A. Metzger
- 👤 Barry A. Maskas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:46
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/88; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1064; G06F11/22; G06F11/2205
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
132 words
A method of managing a cache upon detection of an address TAG parity error, the cache including a plurality of entries for storage of data, and each entry having a corresponding address TAG entry, the method comprising the steps of: performing a TAG parity check for each access to the cache; upon detection of a parity error in an address TAG; disabling allocation of TAG entries for storage of new address TAGs; indicating the TAG parity error to an error correction mechanism; and while said allocation is disabled, allowing access to and modification of data and status bits of said plurality of cache entries such that the cache operates as if no error had been detected with the exception of said disabling allocation of TAG entries for storage of new address TAGS.
Claim 2
Independent Claim
132 words
A method of managing a cache upon detection of an address TAG parity error, the cache including a plurality of entries for storage of data, and each entry having a corresponding address TAG entry, the method comprising the steps of: performing a TAG parity check for each access to the cache; upon detection of a parity error in an address TAG; disabling allocation of TAG entries for storage of new address TAGs; indicating the TAG parity error to an error correction mechanism; and while said allocation is disabled, allowing access to and modification of data and status bits of said plurality of cache entries such that the cache operates as if no error had been detected with the exception of said disabling allocation of TAG entries for storage of new address TAGS.
Claim 3
Dependent Claim
26 words
The method according to claim 1 further comprising the step of: leaving said entry corresponding to said parity error unmodified until said parity error is investigated.
Claim 4
Dependent Claim
20 words
The method of claim 1 wherein said performing, disabling and indicating steps are performed automatically by a bus interface unit.
Claim 5
Dependent Claim
26 words
The method of claim 1 wherein, upon detection of a tag parity error during a system but transaction, the transaction is converted to a no-op transaction.
Claim 6
Dependent Claim
21 words
The method of claim 1 wherein information corresponding the TAG parity error is stored in a control and status register (CSR).
Claim 7
Dependent Claim
50 words
The method of claim 5 wherein a multiple error detected bit is set when additional TAG parity errors are detected subsequent the TAG parity error but prior to correction of the TAG parity error; and wherein information corresponding to the additional TAG parity errors is not stored in the CSR.
Claim 8
Dependent Claim
121 words
A cache memory system including a plurality of entries for storage of data, with each entry having a corresponding address TAG entry, said system comprising: means for performing a TAG parity check for each access to the cache; means for detecting a parity error in an address TAG; means responsive to detection of the parity error for disabling allocation of TAG entries for storage of new address TAGs; means for indicating the TAG parity error to an error correction mechanism; and means for providing continued access to the cache entries prior to correction of the TAG parity error as if no error had been detected with the exception of said disabling allocation of TAG entries for storage of new address TAGs.
Claim 9
Dependent Claim
121 words
A cache memory system including a plurality of entries for storage of data, with each entry having a corresponding address TAG entry, said system comprising: means for performing a TAG parity check for each access to the cache; means for detecting a parity error in an address TAG; means responsive to detection of the parity error for disabling allocation of TAG entries for storage of new address TAGs; means for indicating the TAG parity error to an error correction mechanism; and means for providing continued access to the cache entries prior to correction of the TAG parity error as if no error had been detected with the exception of said disabling allocation of TAG entries for storage of new address TAGs.
Claim 10
Dependent Claim
37 words
The cache memory system of claim 7 wherein the means for providing continued access includes means for altering values of status bits associated with each of said plurality of entries including those entries having TAG parity errors.
Claim 11
Dependent Claim
47 words
The cache memory system of claim 7 wherein said means for providing continued access includes means for updating a cache entry, including those entries having TAG parity errors, in accordance with an update versus invalidate policy when said access results in a hit during a write operation.
Claim 12
Dependent Claim
46 words
The cache memory system of claim 7 wherein said means for providing continued access includes means for supplying data, from a cache entry having no TAG parity error, in response to a read operation resulting in which a cache hit has occurred corresponding to said entry.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-12 | 2000-11-11 | 2001-05-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-12 | 2004-11-11 | 2005-05-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-12 | 2008-11-11 | 2009-05-13 | $7700.00 | Window Closed / Lapsed |