Abstract This invention discloses a synchronous DRAM. An address counter provides a column address of eight bits. The low-order four bits of the column address are assigned to a first column predecoder while the high-order four bits are assigned to a second column predecoder. The first column predecoder provides first predecode signals which are activated in synchronization with a clock leading edge of an internal clock signal and deactivated in synchronization with a clock trailing edge subsequent to the clock leading edge. The second column predecoder provides second predecode signals which make a transition in synchronization with the clock trailing edge. A column decoder sequentially activates column-select lines of a memory cell array according to the AND obtained from all combinations of the first predecode signals and the second predecode signals. Fast, low power column-select line activation is accomplished accordingly.
A semiconductor memory device capable of reading data in a clock-synchronized manner, comprising: a memory cell array wherein, when any one of plural column-select lines are activated, data is read out of a corresponding column of said memory cell array; an address counter for continuously updating column addresses in synchronization with a clock signal and for sequentially providing said column addresses thus updated; a first column predecoder for activating signals generated by decoding plural low-order bits of said column addresses in synchronization with one of two consecutive clock edges of said clock signal, one of which is a clock leading edge and the other of which is a clock trailing edge, for deactivating said signals in synchronization with the other clock edge, and for providing said signals in the form of first predecode signals; a second column predecoder for providing signals generated by decoding plural high-order bits of said column addresses in the form of second predecode signals; and a column decoder for providing AND signals obtained from all combinations of said first predecode signals and said second predecode signals in the form of signals for activation of said plural column-select lines.
Claim 2
Dependent Claim
192 words
A semiconductor memory device capable of reading data in a clock-synchronized manner, comprising: a memory cell array wherein, when any one of plural column-select lines are activated, data is read out of a corresponding column of said memory cell array; an address counter for continuously updating column addresses in synchronization with a clock signal and for sequentially providing said column addresses thus updated; a first column predecoder for activating signals generated by decoding plural low-order bits of said column addresses in synchronization with one of two consecutive clock edges of said clock signal, one of which is a clock leading edge and the other of which is a clock trailing edge, for deactivating said signals in synchronization with the other clock edge, and for providing said signals in the form of first predecode signals; a second column predecoder for providing signals generated by decoding plural high-order bits of said column addresses in the form of second predecode signals; and a column decoder for providing AND signals obtained from all combinations of said first predecode signals and said second predecode signals in the form of signals for activation of said plural column-select lines.
Claim 3
Dependent Claim
45 words
A semiconductor memory device according to claim 1 wherein said first column predecoder has an AND circuit for providing AND signals of signals generated by decoding plural low-order bits of said column addresses and said clock signal, in the form of said first predecode signals.