CMOS transistor network to gate level model extractor for simulation, verification and test generation

Claim 1

A transistor network to gate level model extraction method, comprising: reading in a transistor netlist and user inputs; providing user inputs identifying a particular section of the transistor network to be analyzed; inputting a set of relationships that are not accepted by the transistor network; listing, for every net that drives an input to a transistor, the channel-connected paths that act as inputs to the transistor; determining the conduction status of each path under precharge conditions and evaluating the condition; forming AND gates representing the logical condition under which each path will conduct; using OR gates, OR'ing all AND gate outputs in various groups that represent paths ending at various terminal nodes, e.g., GND, V DD , primary input; based upon the user input, and the output of the OR gates, producing an output such that: if only paths to logic node 0 are turned on, the output will be 0; if only paths to logic node 1 are turned on, the output will be 1; and if the paths to logic nodes 0 and 1 are turned on, the output is based on additional information, including user information, and further analysis of transistor sizes; and if no paths are turned on, producing an appropriate output such as a floating output or X.