Patent US5629637A successfully refreshed from Google Patents.
US5629637A
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Method of time multiplexing a programmable logic device
Assignee: Xilinx Inc
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Filing: 1995-08-18
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Granted: 1997-05-13
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Expires: 2015-08-18
Abstract
Abstract A method of time multiplexing a programmable logic device (PLD) includes inputting a design for the PLD and dividing an evaluation of the logic of the design into a plurality of micro cycles. The method further includes identifying the logic not within a critical path of the design and rescheduling the identified logic for evaluation in other micro cycles. Alternatively, if the PLD includes a plurality of combinational logic elements, the method further includes scheduling a combinational logic element in a micro cycle no earlier than all the combinational logic elements that generate the input signals to said combinational logic element. Further alternatively, if the PLD includes a plurality of combinational logic elements and a plurality of sequential logic elements, the method further includes scheduling a sequential logic element in a micro cycle no earlier than all the combinational logic elements that generate input signals to the sequential logic element and scheduling each sequential logic element in a micro cycle no earlier than all the combinational logic elements or the sequential logic elements that the sequential logic element drives. If the PLD includes a plurality of combinational logic elements, a plurality of sequential logic elements, and a storage device, the method further includes mapping at least one of the sequential logic elements in the design into the storage device and scheduling the plurality of combinational logic elements and the remaining sequential logic elements.
Inventors
- 👤 Stephen M. Trimberger
- 👤 Richard A. Carberry
- 👤 Robert A. Johnson
- 👤 Jennifer Wong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:19
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/17752; H03K19/17704; H03K19/17756
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
71 words
A method of clocking a time multiplexed programmable logic device implementing a user's circuit, said circuit having a fastest clock and at least one other clock, said method comprising: implementing said fastest clock as a user clocks, wherein said user clock defines a cycle during which the output signals for the combinational logic of said circuit are updated; and implementing any other synchronous clock with a micro cycle register enable signal.
Claim 2
Independent Claim
71 words
A method of clocking a time multiplexed programmable logic device implementing a user's circuit, said circuit having a fastest clock and at least one other clock, said method comprising: implementing said fastest clock as a user clocks, wherein said user clock defines a cycle during which the output signals for the combinational logic of said circuit are updated; and implementing any other synchronous clock with a micro cycle register enable signal.
Claim 3
Independent Claim
62 words
A method of clocking a time multiplexed programmable logic device having a fastest clock and at least one other clock, said method comprising: implementing said fastest clock as user clock; and implementing any other synchronous clock with micro cycle register enable signal, wherein said enable signal is active for one cycle of said fastest clock after an edge of a slower clock.
Claim 4
Independent Claim
62 words
A method of clocking a time multiplexed programmable logic device having a fastest clock and at least one other clock, said method comprising: implementing said fastest clock as user clock; and implementing any other synchronous clock with micro cycle register enable signal, wherein said enable signal is active for one cycle of said fastest clock after an edge of a slower clock.
Claim 5
Independent Claim
64 words
A method of time multiplexing a programmable logic device comprising: inputting a design for said programmable logic device; dividing an evaluation of the logic of said design into a plurality of micro cycles; and storing a plurality of intermediate logic states corresponding to said plurality of micro cycles, wherein each intermediate logic state is selectively accessible during each of said plurality of micro cycles.
Claim 6
Independent Claim
64 words
A method of time multiplexing a programmable logic device comprising: inputting a design for said programmable logic device; dividing an evaluation of the logic of said design into a plurality of micro cycles; and storing a plurality of intermediate logic states corresponding to said plurality of micro cycles, wherein each intermediate logic state is selectively accessible during each of said plurality of micro cycles.
Claim 7
Independent Claim
99 words
A method of time multiplexing a programmable logic device comprising: inputting a design for said programmable logic device; providing a plurality of micro cycles for evaluating the logic of said design; identifying the logic within a critical path of said design; scheduling said logic within a critical path in predetermined microcycles; identifying a first micro cycle in said predetermined microcycles in which a portion of the logic not within a critical path of said design is scheduled; and rescheduling said portion in a second micro cycle, wherein said second micro cycle is one of said plurality of micro cycles.
Claim 8
Independent Claim
99 words
A method of time multiplexing a programmable logic device comprising: inputting a design for said programmable logic device; providing a plurality of micro cycles for evaluating the logic of said design; identifying the logic within a critical path of said design; scheduling said logic within a critical path in predetermined microcycles; identifying a first micro cycle in said predetermined microcycles in which a portion of the logic not within a critical path of said design is scheduled; and rescheduling said portion in a second micro cycle, wherein said second micro cycle is one of said plurality of micro cycles.
Claim 9
Independent Claim
70 words
A method of time multiplexing a programmable logic device comprising: inputting a design for said programmable logic device; and dividing an evaluation of the logic of said design into a plurality of micro cycles, wherein the logic of a first micro cycle is evaluated a plurality of times during a user clock cycle, and wherein the logic of a second micro cycle is evaluated once during said user clock cycle.
Claim 10
Independent Claim
70 words
A method of time multiplexing a programmable logic device comprising: inputting a design for said programmable logic device; and dividing an evaluation of the logic of said design into a plurality of micro cycles, wherein the logic of a first micro cycle is evaluated a plurality of times during a user clock cycle, and wherein the logic of a second micro cycle is evaluated once during said user clock cycle.
Claim 11
Independent Claim
60 words
A method of time multiplexing a programmable logic device comprising: inputting a design for said programmable logic device; dividing an evaluation of the logic of said design into a plurality of micro cycles, wherein said step of dividing includes providing a first set of logic every micro cycle and providing a second set of logic only during predetermined micro cycles.
Claim 12
Independent Claim
60 words
A method of time multiplexing a programmable logic device comprising: inputting a design for said programmable logic device; dividing an evaluation of the logic of said design into a plurality of micro cycles, wherein said step of dividing includes providing a first set of logic every micro cycle and providing a second set of logic only during predetermined micro cycles.
Claim 13
Independent Claim
64 words
A method of time multiplexing a programmable logic device comprising: inputting a design for said programmable logic device; determining the order of a plurality of micro cycles to evaluate the logic of said design, wherein said logic includes a plurality of combinational logic elements; and assigning said plurality of combinational logic elements to said plurality of micro cycles based on said step of determining.
Claim 14
Independent Claim
64 words
A method of time multiplexing a programmable logic device comprising: inputting a design for said programmable logic device; determining the order of a plurality of micro cycles to evaluate the logic of said design, wherein said logic includes a plurality of combinational logic elements; and assigning said plurality of combinational logic elements to said plurality of micro cycles based on said step of determining.
Claim 15
Dependent Claim
47 words
The method of claim 7 wherein said logic includes a plurality of combinational logic elements, wherein said method further includes: scheduling a combinational logic element in a micro cycle no earlier than all the combinational logic elements that generate the input signals to said combinational logic element.
Claim 16
Independent Claim
105 words
A method of time multiplexing a programmable logic device comprising: inputting a design for said programmable logic device; dividing an evaluation of the logic of said design into a plurality of micro cycles, wherein said logic includes a plurality of combinational logic elements and a plurality of sequential logic elements; scheduling a sequential logic element in a micro cycle no earlier than all the combinational logic elements that generate input signals to said sequential logic element; and scheduling each sequential logic element in a micro cycle no earlier than all the combinational logic elements or the sequential logic elements that said sequential logic element drives.
Claim 17
Independent Claim
105 words
A method of time multiplexing a programmable logic device comprising: inputting a design for said programmable logic device; dividing an evaluation of the logic of said design into a plurality of micro cycles, wherein said logic includes a plurality of combinational logic elements and a plurality of sequential logic elements; scheduling a sequential logic element in a micro cycle no earlier than all the combinational logic elements that generate input signals to said sequential logic element; and scheduling each sequential logic element in a micro cycle no earlier than all the combinational logic elements or the sequential logic elements that said sequential logic element drives.
Claim 18
Independent Claim
67 words
A method of time multiplexing a programmable logic device comprising: inputting a design for said programmable logic device; dividing an evaluation of the logic of said design into a plurality of micro cycles, further including determining that the number of levels of logic in a critical path of said design is greater than a number of configurations in which the programmable logic device is to be implemented.
Claim 19
Independent Claim
67 words
A method of time multiplexing a programmable logic device comprising: inputting a design for said programmable logic device; dividing an evaluation of the logic of said design into a plurality of micro cycles, further including determining that the number of levels of logic in a critical path of said design is greater than a number of configurations in which the programmable logic device is to be implemented.
Claim 20
Dependent Claim
11 words
The method of claim 10 further including compressing said critical path.
Claim 21
Dependent Claim
19 words
The method of claim 11 wherein said compressing includes bypassing a state storage device on said programmable logic device.
Claim 22
Independent Claim
78 words
A method of time multiplexing a programmable logic device comprising: inputting a design for said programmable logic device; dividing an evaluation of the logic of said design into a plurality of micro cycles; identifying the logic not within a critical path of said design; and rescheduling the identified logic for evaluation in other micro cycles, wherein said rescheduling includes providing late-needed signals for said logic in later microcycles and providing early-needed signals for said logic in earlier microcycles.
Claim 23
Independent Claim
78 words
A method of time multiplexing a programmable logic device comprising: inputting a design for said programmable logic device; dividing an evaluation of the logic of said design into a plurality of micro cycles; identifying the logic not within a critical path of said design; and rescheduling the identified logic for evaluation in other micro cycles, wherein said rescheduling includes providing late-needed signals for said logic in later microcycles and providing early-needed signals for said logic in earlier microcycles.
Claim 24
Independent Claim
76 words
A method of time multiplexing a programmable logic device including a storage device, said method comprising: inputting a design for said programmable logic device; dividing an evaluation of the logic of said design into a plurality of micro cycles, wherein said logic includes a plurality of combinational logic elements and at least one sequential logic element; scheduling said plurality of combinational logic elements; and mapping said at least one sequential logic element into said storage device.
Claim 25
Independent Claim
76 words
A method of time multiplexing a programmable logic device including a storage device, said method comprising: inputting a design for said programmable logic device; dividing an evaluation of the logic of said design into a plurality of micro cycles, wherein said logic includes a plurality of combinational logic elements and at least one sequential logic element; scheduling said plurality of combinational logic elements; and mapping said at least one sequential logic element into said storage device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-12 | 2000-11-11 | 2001-05-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-12 | 2004-11-11 | 2005-05-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-12 | 2008-11-11 | 2009-05-13 | $7700.00 | Window Closed / Lapsed |