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US5629557A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device capable of preventing humidity invasion

Assignee: Yamaha Corp
•
Filing: 1996-03-25
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Granted: 1997-05-13
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Expires: 2016-03-25
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Abstract

Abstract In an IC chip having an interlevel insulation film constituted by a first level silicon oxide film, a spin-on-glass film, a second level silicon oxide film, the SOG film is partially removed in a buffer region of a closed loop shape inside of the chip periphery and surrounding the chip inner region. The second level silicon oxide film and a passivation insulation film are formed covering the SOG film and buffer region. Water contents are intercepted by the buffer region and will not reach the element region. It is therefore possible to prevent an inversion of the conductivity type at the surface of a well region in the element region or a corrosion of wiring layers, thereby improving the reliability of an IC device.

Inventors

  • 👤 Takahisa Yamaha

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 03:13
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/45; H10W20/48; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283; H10P50/286; H10P50/287; Y; Y10; Y10S; Y10S148/00; Y10S148/028

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 81 words
A semiconductor wafer, comprising: a) a plurality of semiconductor chip regions, comprising: (1) device regions to form a device structure thereon, the device structure having electrodes electrically connected to active regions provided therein; and (2) a buffer region provided on a periphery of the device region; and b) an insulating layer having moisture permeability for electrically insulating the electrodes therebetween, the insulating layer being formed over the device regions while being removed from a buffer region of the semiconductor chip regions.
Claim 2
Dependent Claim 81 words
A semiconductor wafer, comprising: a) a plurality of semiconductor chip regions, comprising: (1) device regions to form a device structure thereon, the device structure having electrodes electrically connected to active regions provided therein; and (2) a buffer region provided on a periphery of the device region; and b) an insulating layer having moisture permeability for electrically insulating the electrodes therebetween, the insulating layer being formed over the device regions while being removed from a buffer region of the semiconductor chip regions.
Claim 3
Dependent Claim 30 words
A semiconductor wafer according to claim 1, further comprising: (c) scribe regions provided between the plurality of semiconductor chip regions, the buffer region being separately provided from the scribe regions.
Claim 4
Dependent Claim 18 words
A semiconductor wafer according to claim 1, wherein the buffer region has a width of about 50 micrometers.
Claim 5
Dependent Claim 59 words
A semiconductor wafer according to claim 1, wherein the insulating layer comprising: (1) a first insulating layer deposited over the device region; (2) a second insulating layer deposited over the insulating layer and having moisture permeability, wherein the second insulating layer being removed in the buffer region; and (3) a third insulating layer deposited over the second insulating layer.
Claim 6
Dependent Claim 17 words
A semiconductor wafer according to claim 4, wherein the first and third insulating layer comprise silicon dioxide.
Claim 7
Dependent Claim 14 words
A semiconductor wafer according to claim 4, wherein the second insulating layer comprises spin-on-glass.
Claim 8
Dependent Claim 99 words
A semiconductor wafer comprising: (a) a plurality of semiconductor chip regions, comprising: (1) device regions to form a device structure thereon; and (2) a buffer region provided on a periphery of the device regions; and (b) a laminated insulating layer structure formed over the semiconductor chip regions, but not over the buffer region, said laminated insulating layer structure comprising: (1) a first insulating sublayer deposited over the semiconductor region: (2) a second insulating sublayer deposited over the first insulating sublayer, the second insulating sublayer having moisture permeability; and (3) a third insulating sublayer deposited over the second insulating sublayer.
Claim 9
Dependent Claim 99 words
A semiconductor wafer comprising: (a) a plurality of semiconductor chip regions, comprising: (1) device regions to form a device structure thereon; and (2) a buffer region provided on a periphery of the device regions; and (b) a laminated insulating layer structure formed over the semiconductor chip regions, but not over the buffer region, said laminated insulating layer structure comprising: (1) a first insulating sublayer deposited over the semiconductor region: (2) a second insulating sublayer deposited over the first insulating sublayer, the second insulating sublayer having moisture permeability; and (3) a third insulating sublayer deposited over the second insulating sublayer.
Claim 10
Dependent Claim 29 words
A semiconductor wafer according to claim 7, further comprising: (c) scribe regions provided between the plurality of semiconductor-chip regions, the buffer region being separately provided from the scribe regions.
Claim 11
Dependent Claim 18 words
A semiconductor wafer according to claim 7, wherein the buffer region has a width of about 50 micrometer.
Claim 12
Dependent Claim 17 words
A semiconductor wafer according to claim 7, wherein the first and third insulating layers comprise silicon dioxide.
Claim 13
Dependent Claim 14 words
A semiconductor wafer according to claim 7, wherein the second insulating layer comprises spin-on-glass.

References Cited (Backward Citations)

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3.5 Years (Year 4) 2000-05-12 2000-11-11 2001-05-13 $2000.00 Window Closed / Lapsed
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