Apparatus and method for adapting a computer system to different architectures

Claim 2

A computer system mounted on a motherboard, comprising: a first bus mounted on the motherboard, the first bus for communicating processor address, data, and control signals according to any one of a plurality of different processor architectures; a second bus mounted on the motherboard, the second bus for communicating input/output address, data, and control signals for a peripheral device, the first bus and the second bus decoupled from communicating with each other; a memory module mounted on the first bus, the memory module for storing data; an input/output module mounted on the second bus, the input/output module for connecting to the peripheral device; a processor module mounted on the first and second bus, the processor module for processing the processor and input/output signals, the processor module including a central processing unit, the central processing unit defining the processor address, data, and control signals of the first bus according to one of the plurality of different processor architectures, the processor module including a bridge to interface the processor address, data, and control signals with the input/output address, data, and control signals.

Claim 3

The computer system as in claim 1 wherein the bridge electrically couples the first bus and the second bus.

Claim 4

A computer system for different processor architectures mounted on a motherboard, comprising: a first bus mounted on the motherboard, the first bus for communicating processor address, data, and control signals according to any one of a plurality of different processor architectures; a second bus mounted on the motherboard, the second bus for communicating input/output address, data, and control signals for a peripheral device, the first bus and the second bus decoupled from communicating with each other; a memory module mounted on the first bus, the memory module for storing data; an input/output module mounted on the second bus, the input/output module for connecting to the peripheral device; a processor module mounted on the first bus and the second bus, the processor module including a central processing unit, the central processing unit defining the processor address, data, and control signals according to one of the plurality of different processor architectures, the processor module to couple the central processing unit to the first bus; and a bridge mounted on the processor module to interface the processor address, data, and control signals and the input/output address, data, and control signals.

Claim 5

A computer system for different processor architectures mounted on a motherboard, comprising: a first bus mounted on the motherboard, the first bus for communicating processor address, data, and control signals according to any one of a plurality of different processor architectures; a second bus mounted on the motherboard, the second bus for communicating input/output address, data, and control signals for a peripheral device, the first bus and the second bus decoupled from communicating with each other; a memory module mounted on the first bus, the memory module for storing data; an input/output module mounted on the second bus, the input/output module for connecting to the peripheral device; a processor module mounted on the first bus and the second bus, the processor module including a central processing unit, the central processing unit defining the processor address, data, and control signals according to one of the plurality of different processor architectures, the processor module to couple the central processing unit to the first bus; and a bridge mounted on the processor module to interface the processor address, data, and control signals and the input/output address, data, and control signals.

Claim 6

The computer system as in claim 3 wherein the bridge electrically couples the first bus and the second bus.