US5625802A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus and method for adapting a computer system to different architectures
Assignee: Samsung Electronics Co Ltd
•
Filing: 1994-12-12
•
Granted: 1997-04-29
•
Expires: 2014-12-12
Abstract
Abstract In a computer system, a mother-board is used to physically connect processor, memory, and input/output modules. The mother-board includes an adaptable processor bus for connecting the processor and memory modules, and an input/output bus for connecting the input/output modules, the processor and input/output bus are decoupled for communicating. A processor module including a bridge is used to coupled the processor and input/output buses, and to adapt the processor bus to a particular processor architectures.
Inventors
- 👤 Hoe T. Cho
- 👤 Maw Z. Jau
- 👤 W. Hugh Durdan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:34
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/409
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
180 words
A computer system mounted on a motherboard, comprising: a first bus mounted on the motherboard, the first bus for communicating processor address, data, and control signals according to any one of a plurality of different processor architectures; a second bus mounted on the motherboard, the second bus for communicating input/output address, data, and control signals for a peripheral device, the first bus and the second bus decoupled from communicating with each other; a memory module mounted on the first bus, the memory module for storing data; an input/output module mounted on the second bus, the input/output module for connecting to the peripheral device; a processor module mounted on the first and second bus, the processor module for processing the processor and input/output signals, the processor module including a central processing unit, the central processing unit defining the processor address, data, and control signals of the first bus according to one of the plurality of different processor architectures, the processor module including a bridge to interface the processor address, data, and control signals with the input/output address, data, and control signals.
Claim 2
Dependent Claim
180 words
A computer system mounted on a motherboard, comprising: a first bus mounted on the motherboard, the first bus for communicating processor address, data, and control signals according to any one of a plurality of different processor architectures; a second bus mounted on the motherboard, the second bus for communicating input/output address, data, and control signals for a peripheral device, the first bus and the second bus decoupled from communicating with each other; a memory module mounted on the first bus, the memory module for storing data; an input/output module mounted on the second bus, the input/output module for connecting to the peripheral device; a processor module mounted on the first and second bus, the processor module for processing the processor and input/output signals, the processor module including a central processing unit, the central processing unit defining the processor address, data, and control signals of the first bus according to one of the plurality of different processor architectures, the processor module including a bridge to interface the processor address, data, and control signals with the input/output address, data, and control signals.
Claim 3
Dependent Claim
19 words
The computer system as in claim 1 wherein the bridge electrically couples the first bus and the second bus.
Claim 4
Dependent Claim
187 words
A computer system for different processor architectures mounted on a motherboard, comprising: a first bus mounted on the motherboard, the first bus for communicating processor address, data, and control signals according to any one of a plurality of different processor architectures; a second bus mounted on the motherboard, the second bus for communicating input/output address, data, and control signals for a peripheral device, the first bus and the second bus decoupled from communicating with each other; a memory module mounted on the first bus, the memory module for storing data; an input/output module mounted on the second bus, the input/output module for connecting to the peripheral device; a processor module mounted on the first bus and the second bus, the processor module including a central processing unit, the central processing unit defining the processor address, data, and control signals according to one of the plurality of different processor architectures, the processor module to couple the central processing unit to the first bus; and a bridge mounted on the processor module to interface the processor address, data, and control signals and the input/output address, data, and control signals.
Claim 5
Dependent Claim
187 words
A computer system for different processor architectures mounted on a motherboard, comprising: a first bus mounted on the motherboard, the first bus for communicating processor address, data, and control signals according to any one of a plurality of different processor architectures; a second bus mounted on the motherboard, the second bus for communicating input/output address, data, and control signals for a peripheral device, the first bus and the second bus decoupled from communicating with each other; a memory module mounted on the first bus, the memory module for storing data; an input/output module mounted on the second bus, the input/output module for connecting to the peripheral device; a processor module mounted on the first bus and the second bus, the processor module including a central processing unit, the central processing unit defining the processor address, data, and control signals according to one of the plurality of different processor architectures, the processor module to couple the central processing unit to the first bus; and a bridge mounted on the processor module to interface the processor address, data, and control signals and the input/output address, data, and control signals.
Claim 6
Dependent Claim
19 words
The computer system as in claim 3 wherein the bridge electrically couples the first bus and the second bus.
References Cited (Backward Citations)
US4328577A
Cited
US4538033A
Cited
US4777615A
Cited
US5299193A
Cited
US5305317A
Cited
US5305442A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-28 | 2000-10-28 | 2001-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-28 | 2004-10-28 | 2005-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-28 | 2008-10-28 | 2009-04-29 | $7700.00 | Window Closed / Lapsed |