Abstract A bit line structure is disclosed. Which includes: sense amplifiers each connected to two pairs of bit lines BL and /BL through bit line selecting switches, to the bit line a plurality of cells are connected, includes: a first bit line pair BL and /BL and a second bit line pair BL and /BL formed by dividing a bit line disposed within a same column respectively in a cell array; a first connecting bit line for connecting the bit line BL of said second bit line pair to said sense amplifier; a second connecting bit line for connecting the bit line /BL of said second bit line pair to said sense amplifier; said second connecting bit line having two crossing sections 25 crossing with another second connecting bit line for connecting a bit line BL of a second bit line belonging to an adjacent sense amplifier; and bit line selecting switches for connecting said first bit line pair and said second bit line pair respectively to said sense amplifier, whereby a number of memory cells connected to each bit line is reduced to 1/2 compared with the conventional technique, the bit lines are arranged 3-dimensionally to eliminate the area loss in carrying out the layout, and particularly, the connecting bit lines are made of a conductive material which has a smaller resistance than a conductive material of the bit lines.
Inventors
👤 Jin-Hong Ahn
👤 Tae-Hyoung Kim
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-11-04 12:59
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/18
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
154 words
A bit line structure having sense amplifiers, each sense amplifier being connected to two pairs of bit lines BL and /BL through bit line selecting switches, and each bit line being connected to a plurality of cells, comprising: a first bit line pair BL and /BL and a second bit line pair BL and /BL formed by dividing a bit line disposed within a same column respectively in a cell array; a first connecting bit line for connecting the bit line BL of said second bit line pair to said sense amplifier; a second connecting bit line for connecting the bit line /BL of said second bit line pair to said sense amplifier; and bit line selecting switches for connecting said first bit line pair and said second bit line pair respectively to said sense amplifier, wherein the first connecting bit line and the second connecting bit line pass over the first bit lines.
Claim 2
Dependent Claim
154 words
A bit line structure having sense amplifiers, each sense amplifier being connected to two pairs of bit lines BL and /BL through bit line selecting switches, and each bit line being connected to a plurality of cells, comprising: a first bit line pair BL and /BL and a second bit line pair BL and /BL formed by dividing a bit line disposed within a same column respectively in a cell array; a first connecting bit line for connecting the bit line BL of said second bit line pair to said sense amplifier; a second connecting bit line for connecting the bit line /BL of said second bit line pair to said sense amplifier; and bit line selecting switches for connecting said first bit line pair and said second bit line pair respectively to said sense amplifier, wherein the first connecting bit line and the second connecting bit line pass over the first bit lines.
Claim 3
Dependent Claim
32 words
The bit line structure as claimed in claim 1, wherein said first and second connecting bit lines are composed of a material different from that of said first and second bit lines.
Claim 4
Dependent Claim
17 words
A semiconductor memory device having a bit line structure of any one of claims 2 and 1.