Patent US5625544A successfully refreshed from Google Patents.
US5625544A
Expired / Lapsed
US
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Charge pump
Assignee: CHINGIS TECHNOLOGY Corp
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Filing: 1996-04-25
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Granted: 1997-04-29
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Expires: 2016-04-25
Abstract
Abstract A charge pump circuit including N stages of diode-capacitor voltage multipliers clocked so as to convert a low voltage received from a supply voltage to a high voltage at an output terminal thereof employs an output stage to improve the efficiency of the charge pump. The output stage includes first and second legs each coupled to the output terminal, where the first leg provides current to the output terminal during low transitions of the clock signal and the second stage provides current to the output terminal during high transitions of the clock signal. In some embodiments, the numerous one of the above-mentioned charge pump circuit may be connected in parallel to achieve even greater output currents. Thus, unlike conventional charge pump circuits, a substantially constant current is provided to the output terminal throughout the period of the clock signal, thereby increasing the average total current provided to the output terminal and, thus, increasing the driving capability of the charge pump circuit.
Inventors
- 👤 Vikram Kowshik
- 👤 Andy Teng-Feng Yu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 07:19
CPC Classifications
H; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/06; H02M3/07; H02M3/073
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
87 words
A charge pump circuit comprising: a clock control circuit for providing a clock signal and an inverted clock signal, said inverted clock signal being approximately 180 degrees out-of-phase with respect to said clock signal; a plurality of diode-capacitor voltage multipliers connected in a chain, wherein alternate ones of said voltage multipliers are coupled to said respective clock and inverted clock signals; and an output stage for providing to an output terminal of said charge pump circuit current during both low and high transitions of said clock signal.
Claim 2
Dependent Claim
87 words
A charge pump circuit comprising: a clock control circuit for providing a clock signal and an inverted clock signal, said inverted clock signal being approximately 180 degrees out-of-phase with respect to said clock signal; a plurality of diode-capacitor voltage multipliers connected in a chain, wherein alternate ones of said voltage multipliers are coupled to said respective clock and inverted clock signals; and an output stage for providing to an output terminal of said charge pump circuit current during both low and high transitions of said clock signal.
Claim 3
Dependent Claim
47 words
The circuit of claim 1, wherein said output stage comprises: first and second substages, said first substage providing current to said output terminal on high transitions of said clock signal, said second substage providing current to said output terminal on high transitions of said inverted clock signal.
Claim 4
Dependent Claim
57 words
The circuit of claim 2, wherein said first substage of said output stage further comprises: a first diode having a cathode coupled to said output terminal and having an anode; and a first capacitor having a first plate coupled to said anode of said first diode and having a second plate coupled to receive said clock signal.
Claim 5
Dependent Claim
79 words
The circuit of claim 3, wherein said second substage of said output stage further comprises: a second diode coupled between a first node and said output terminal; and a second capacitor having a first plate coupled to said first node and having a second plate coupled to receive said inverted clock signal, wherein a third diode is coupled between said first node and the commonly coupled first plate of said first capacitor and said anode of said first diode.
Claim 6
Dependent Claim
49 words
The circuit of claim 4, further comprising: a third capacitor having a first plate coupled to the last diode-capacitor voltage multiplier and having a second plate coupled to receive said clock signal; and a fourth diode coupled between said first plate of said third capacitor and said first node.
Claim 7
Dependent Claim
19 words
The circuit of claim 5, wherein the last diode-capacitor voltage multiplier is coupled to receive said inverted clock signal.
Claim 8
Dependent Claim
12 words
The circuit of claim 2, wherein said diodes comprise diode-connected PMOS transistors.
Claim 9
Dependent Claim
57 words
The circuit of claim 2, wherein said each of said diodes comprises: a P type substrate; an N-well formed in said P type substrate; and P+ and N+ regions formed in said N-well, said P+ region serving as an anode, said N-well serving as a cathode, and said N+ region serving as a contact for said cathode.
Claim 10
Dependent Claim
66 words
The circuit of claim 2, wherein said each of said diodes comprises: a P type substrate; a deep N-well region formed in said P type substrate; a P-well formed in said deep N-well; and P+ and N+ regions formed in said P-well, said N+ region serving as a cathode, said P-well serving as an anode, and said P+ region serving as a contact for said anode.
Claim 11
Dependent Claim
16 words
The circuit of claim 2, wherein said clock and inverted clock signals have non-overlapping high transitions.
Claim 12
Dependent Claim
132 words
A charge pump circuit comprising: a clock control circuit for providing a plurality of clock signals and a plurality of associated inverted clock signals, wherein each of said inverted clock signals is approximately 180 degrees out-of-phase with respect to its associated clock signal; a plurality voltage multiplier circuits, said voltage multiplier circuits each comprising a plurality of series connected diode-capacitor voltage multipliers, wherein the capacitors of each of said plurality of voltage multiplier circuits are alternately coupled to a selected one of said plurality of said clock signals and to an inverted clock signal associated with said selected one of said clock signals; and a plurality of output stages for providing to an output terminal of said charge pump circuit substantially equal current during low and high transitions of said clock signals.
Claim 13
Dependent Claim
132 words
A charge pump circuit comprising: a clock control circuit for providing a plurality of clock signals and a plurality of associated inverted clock signals, wherein each of said inverted clock signals is approximately 180 degrees out-of-phase with respect to its associated clock signal; a plurality voltage multiplier circuits, said voltage multiplier circuits each comprising a plurality of series connected diode-capacitor voltage multipliers, wherein the capacitors of each of said plurality of voltage multiplier circuits are alternately coupled to a selected one of said plurality of said clock signals and to an inverted clock signal associated with said selected one of said clock signals; and a plurality of output stages for providing to an output terminal of said charge pump circuit substantially equal current during low and high transitions of said clock signals.
Claim 14
Dependent Claim
49 words
The circuit of claim 11, wherein each of said output stages comprises first and second substages, said first substage providing current to said output terminal on high transitions of said clock signal, said second substage providing current to said output terminal on high transitions of said inverted clock signal.
Claim 15
Dependent Claim
57 words
The circuit of claim 12, wherein said first substage of said output stage further comprises: a first diode having a cathode coupled to said output terminal and having an anode; and a first capacitor having a first plate coupled to said anode of said first diode and having a second plate coupled to receive said clock signal.
Claim 16
Dependent Claim
79 words
The circuit of claim 13, wherein said second substage of said output stage further comprises: a second diode coupled between a first node and said output terminal; and a second capacitor having a first plate coupled to said first node and having a second plate coupled to receive said inverted clock signal, wherein a third diode is coupled between said first node and the commonly coupled first plate of said first capacitor and said anode of said first diode.
Claim 17
Dependent Claim
49 words
The circuit of claim 14, further comprising: a third capacitor having a first plate coupled to the last diode-capacitor voltage multiplier and having a second plate coupled to receive said clock signal; and a fourth diode coupled between said first plate of said third capacitor and said first node.
Claim 18
Dependent Claim
19 words
The circuit of claim 15, wherein the last diode-capacitor voltage multiplier is coupled to receive said inverted clock signal.
Claim 19
Dependent Claim
12 words
The circuit of claim 12, wherein said diodes comprise diode-connected PMOS transistors.
Claim 20
Dependent Claim
57 words
The circuit of claim 12, wherein said each of said diodes comprises: a P type substrate; an N-well formed in said P type substrate; and P+ and N+ regions formed in said N-well, said P+ region serving as an anode, said N-well serving as a cathode, and said N+ region serving as a contact for said cathode.
Claim 21
Dependent Claim
66 words
The circuit of claim 12, wherein said each of said diodes comprises: a P type substrate; a deep N-well region formed in said P type substrate; a P-well formed in said deep N-well; and P+ and N+ regions formed in said P-well, said N+ region serving as a cathode, said P-well serving as an anode, and said P+ region serving as a contact for said anode.
Claim 22
Dependent Claim
16 words
The circuit of claim 12, wherein said clock and inverted clock signals have non-overlapping high transitions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-28 | 2000-10-28 | 2001-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-28 | 2004-10-28 | 2005-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-28 | 2008-10-28 | 2009-04-29 | $7700.00 | Window Closed / Lapsed |