US5625379A
Expired / Lapsed
US
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Video processing apparatus systems and methods
Assignee: S3 Graphics Co Ltd
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Filing: 1995-03-13
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Granted: 1997-04-29
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Expires: 2015-03-13
Abstract
Abstract A display interface device 20 is provided which includes inputs for receiving video data words, the video data words including control codes for controlling the output format of a display, and a video clock signal received from an associated video controller. A first-in/first-out memory 30 is also provided with a video data word clocked into memory 30 by the first clock and clocked out of memory 30 by a second clock generated from a clock received from an associated graphics controller.
Inventors
- 👤 Christopher L. Reinert
- 👤 Sudhir Sharma
- 👤 Robert M. Nally
- 👤 John C. Schafer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 01:11
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/64; H04N9/641; G; G09; G09G; G09G5/00; G09G5/003; G09G5/006; G09G5/008; G09G5/02; G09G5/06; G09G5/08; G09G5/36; G09G5/363; G09G5/39; G09G5/391; G09G5/395; G09G5/40; G09G2310/00; G09G2310/02; G09G2310/0232; G09G2320/00; G09G2320/06; G09G2320/0606; G09G2320/0673; G09G2340/00; G09G2340/04; G09G2340/0407; G09G2340/12; G09G2340/125
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
197 words
Video data processing circuitry comprising: a memory, for storing video data words and associated control codes, input of said video data words synchronized to a first time base established by an associated video processor and output of said video data words synchronized with a second time base established by an associated graphics processor; format alignment circuitry coupled to said memory and operable to receive a said video data words output from said memory in a first format and align the said video data words into a second format; chrominance interpolator circuitry coupled to said format alignment circuitry and operable to receive from said format alignment circuitry a said video data word in YUV format of a predetermined number of bits and provide in response an interpolated YUV data word of a greater number of bits; a decoder operable to receive ones of said video data words output from said chrominance interpolator circuitry in a YUV format and output RGB color data words defining selected display pixels in response; and a scaler operable to receive said RGB words output from said decoder and said associated control codes and provide in response RGB data words defining other display pixels.
Claim 2
Dependent Claim
197 words
Video data processing circuitry comprising: a memory, for storing video data words and associated control codes, input of said video data words synchronized to a first time base established by an associated video processor and output of said video data words synchronized with a second time base established by an associated graphics processor; format alignment circuitry coupled to said memory and operable to receive a said video data words output from said memory in a first format and align the said video data words into a second format; chrominance interpolator circuitry coupled to said format alignment circuitry and operable to receive from said format alignment circuitry a said video data word in YUV format of a predetermined number of bits and provide in response an interpolated YUV data word of a greater number of bits; a decoder operable to receive ones of said video data words output from said chrominance interpolator circuitry in a YUV format and output RGB color data words defining selected display pixels in response; and a scaler operable to receive said RGB words output from said decoder and said associated control codes and provide in response RGB data words defining other display pixels.
Claim 3
Dependent Claim
12 words
The processing circuitry of claim 1 wherein said scaler comprises an x-scaler.
Claim 4
Dependent Claim
22 words
The processing circuitry of claim 1 wherein said first time base is based on a video clock received from said video processor.
Claim 5
Dependent Claim
24 words
The processing circuitry of claim 1 wherein said second time base is based on a pixel clock received from an external graphics processing source.
Claim 6
Dependent Claim
19 words
The processing circuitry of claim 1 wherein data flow through said decoder is synchronized with said second time base.
Claim 7
Dependent Claim
19 words
The processing circuitry of claim 1 wherein data flow through said scaler is synchronized with said second time base.
Claim 8
Dependent Claim
20 words
The processing circuitry of claim 1 wherein data flow through said format aligner is synchronized with said second time base.
Claim 9
Dependent Claim
21 words
The processing circuitry of claim 1 wherein data flow through said chrominance interpolator circuitry is synchronized with said second time base.
Claim 10
Dependent Claim
14 words
The processing circuitry of claim 1 wherein said scaler performs scaling using linear interpolation.
Claim 11
Dependent Claim
194 words
A display system comprising: a display operable to display images as fields of a plurality of pixels, the display of said pixels timed with a pixel clock; a graphics data source operable to generate graphics data defining pixels in a said field; graphics processing circuitry operable to process said graphics data received from said graphics data source and provide in response signals for driving said display; a video data source operable to generate video data defining pixels in a said field and a video clock; and an interface for interfacing said graphics data source and said video data source to said display, comprising: a memory operable to store video data words received from said video memory, a write of a said video data word into said memory clocked by said video clock; video processing circuitry operable to process said video data received from said memory and provide signals for driving said display in response, a read of a said video data word out of said memory, clocked by said pixel clock; and mixing circuitry for selecting between said signals generated by said video processing circuitry and said signals generated by said graphics processing circuitry.
Claim 12
Dependent Claim
194 words
A display system comprising: a display operable to display images as fields of a plurality of pixels, the display of said pixels timed with a pixel clock; a graphics data source operable to generate graphics data defining pixels in a said field; graphics processing circuitry operable to process said graphics data received from said graphics data source and provide in response signals for driving said display; a video data source operable to generate video data defining pixels in a said field and a video clock; and an interface for interfacing said graphics data source and said video data source to said display, comprising: a memory operable to store video data words received from said video memory, a write of a said video data word into said memory clocked by said video clock; video processing circuitry operable to process said video data received from said memory and provide signals for driving said display in response, a read of a said video data word out of said memory, clocked by said pixel clock; and mixing circuitry for selecting between said signals generated by said video processing circuitry and said signals generated by said graphics processing circuitry.
Claim 13
Dependent Claim
17 words
The system of claim 10 wherein said graphics data source is operable to generate said pixel clock.
Claim 14
Dependent Claim
46 words
The device of claim 10 wherein said video processing circuitry includes format alignment circuitry operable to receive words of said video data coupled thereto from said memory in a first bit format and output said ones of said video data words in a second bit format.
Claim 15
Dependent Claim
32 words
The device of claim 10 wherein said video processing circuitry includes interpolation circuitry operable to receive words of said video in a YUV format provide interpolated words of YUQ data in response.
Claim 16
Dependent Claim
33 words
The device of claim 10 wherein said video processing circuitry includes conversion circuitry operable to receive words of said video data in a YUV format and convert said words to an RGB format.
Claim 17
Dependent Claim
67 words
The device of claim 10 wherein words of said video data define selected pixels in a said field, said selected pixels spaced apart in said field by other ones of said pixels in said field, said video processing circuitry further comprising scaling circuitry operable to receive said words video data defining said selected pixels and provide in response data words defining said other ones of said pixels.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-28 | 2000-10-28 | 2001-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-28 | 2004-10-28 | 2005-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-28 | 2008-10-28 | 2009-04-29 | $7700.00 | Window Closed / Lapsed |