US5625299A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiple lead analog voltage probe with high signal integrity over a wide band width
Assignee: Agilent Technologies Inc
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Filing: 1995-02-03
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Granted: 1997-04-29
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Expires: 2015-02-03
Abstract
Abstract A probe head includes integrated circuit chip inputs, a ground plane on a circuit board, and hundreds of probe leads comprising traces on the circuit board connected between the inputs and a circuit under test. Each trace is about 3 mils wide. There is a DICLAD polytetrafluoroethylene dielectric material of dielectric constant of about 2.2 between the ground and traces. Every other trace is electrically connected to the ground plane. Input resistors are buried in the circuit board and there is an on-chip input divider network. The customer defines the grounded pins of a circuit to be tested. Probe leads corresponding to the grounded pins are connected to the ground plane, maximizing the connections between the grounds of the probe and the circuit under test and minimizing unequal ground potentials.
Inventors
- 👤 Thomas F. Uhling
- 👤 David J. Dascher
- 👤 Keith C. Griggs
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 13:16
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2886; G01R1/00; G01R1/02; G01R1/06; G01R1/067; G01R1/073; G01R31/2832; G01R31/2836; G01R31/2844; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49004; Y10T29/49117; Y10T29/49124; Y10T29/49147
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
124 words
An analog voltage probe comprising: an integrated circuit having a plurality of IC inputs, an output, and an analog amplifier connectable between said inputs and said output; a circuit board having a probe ground including a ground plane; a plurality of input leads, one end of each lead connected to one of said IC inputs and the other end adapted to be connected to a circuit under test, each lead comprising a trace on said circuit board, each trace being from 0.5 mils to 5 mils wide; and said circuit board further including a dielectric material between said ground plane and said traces, said dielectric material having a dielectric constant of 5 or less and a thickness of between 4 mils and 6 mils.
Claim 2
Dependent Claim
124 words
An analog voltage probe comprising: an integrated circuit having a plurality of IC inputs, an output, and an analog amplifier connectable between said inputs and said output; a circuit board having a probe ground including a ground plane; a plurality of input leads, one end of each lead connected to one of said IC inputs and the other end adapted to be connected to a circuit under test, each lead comprising a trace on said circuit board, each trace being from 0.5 mils to 5 mils wide; and said circuit board further including a dielectric material between said ground plane and said traces, said dielectric material having a dielectric constant of 5 or less and a thickness of between 4 mils and 6 mils.
Claim 3
Dependent Claim
55 words
An analog test probe as in claim 1, and further including a plurality of intermediate leads, each intermediate lead located between an adjacent pair of said input leads, each of said intermediate leads connected to said probe ground, whereby each of said input leads is separated from adjacent input leads by a grounded intermediate lead.
Claim 4
Dependent Claim
14 words
An analog test probe as in claim 1 wherein said dielectric constant is 2.2.
Claim 5
Dependent Claim
14 words
An analog test probe as in claim 1 wherein said dielectric material comprises polytetrafluoroethylene.
Claim 6
Dependent Claim
15 words
An analog test probe as in claim 4 wherein said dielectric material comprises DICLAD polytetrafluoroethylene.
Claim 7
Dependent Claim
23 words
An analog test probe as in claim 1 wherein each of said input leads further comprises a resistor buried in said circuit board.
Claim 8
Dependent Claim
29 words
An analog test probe as in claim 1 and further including a plurality of on-chip input divider networks each of said networks connected to one of said input leads.
Claim 9
Dependent Claim
21 words
An analog voltage probe as in claim 1 wherein selected ones of said input leads are connected to said probe ground.
Claim 10
Dependent Claim
96 words
An analog voltage probe comprising: a plurality of probe inputs, an output, and an analog amplifier connectable between said inputs and said output; a circuit board including a probe ground; a plurality of input leads connected between said inputs and said amplifier, each lead comprising a trace on said circuit board; and a plurality of intermediate leads, each intermediate lead located between an adjacent pair of said input leads, each of said intermediate leads connected to said probe ground, whereby each of said input leads is separated from adjacent input leads by a grounded intermediate lead.
Claim 11
Dependent Claim
96 words
An analog voltage probe comprising: a plurality of probe inputs, an output, and an analog amplifier connectable between said inputs and said output; a circuit board including a probe ground; a plurality of input leads connected between said inputs and said amplifier, each lead comprising a trace on said circuit board; and a plurality of intermediate leads, each intermediate lead located between an adjacent pair of said input leads, each of said intermediate leads connected to said probe ground, whereby each of said input leads is separated from adjacent input leads by a grounded intermediate lead.
Claim 12
Dependent Claim
21 words
An analog voltage probe as in claim 9 wherein selected ones of said input leads are connected to said probe ground.
Claim 13
Dependent Claim
25 words
An analog test probe as in claim 9 wherein said probe includes an integrated circuit and said analog amplifier is located in said integrated circuit.
Claim 14
Dependent Claim
26 words
An analog test probe as in claim 9 wherein said probe ground includes a current return ground to remove high frequency current from the probe circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-28 | 2000-10-28 | 2001-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-28 | 2004-10-28 | 2005-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-28 | 2008-10-28 | 2009-04-29 | $7700.00 | Window Closed / Lapsed |