Programmable semiconductor device using anti-fuse elements with floating electrode

Claim 2

An anti-fuse element in a semiconductor device including a semiconductor substrate, comprising: an insulator layer formed over the substrate; at least two wiring lines formed on the insulator layer, predetermined portions of the at least two wiring lines being in proximity to each other at a node; a dielectric anti-fuse film formed on the two wiring lines at the node; a floating electrode formed on the dielectric anti-fuse film to overlap the predetermined portions of the at least two wiring lines at the node, and having no direct contact with a potential source; and at least one additional layer inserted between the insulator layer and the semiconductor substrate, the additional layer having no direct contact with the floating electrode at the node, wherein upon application of a destructive electric potential difference across the at least two wiring lines, the dielectric anti-fuse film breaks down and conductive paths are respectively formed between the floating electrode and each of the at least two wiring lines.

Claim 3

An anti-fuse element according to claim 1, wherein the dielectric anti-fuse film comprises at least one of Si, compounds including Si and N, and compounds including Si and O.

Claim 4

An anti-fuse element according to claim 2, wherein the dielectric anti-fuse film further comprises at least one of H, F, Cl.

Claim 5

An anti-fuse element according to claim 1, wherein the dielectric anti-fuse film comprises a material selected from a group consisting of undoped amorphous silicon, undoped polycrystalline silicon, and an oxide metal film comprising one of Al, Cu, Ti, W, Mo.

Claim 6

An anti-fuse element according to claim 1, wherein the floating electrode comprises a material selected from a group consisting of doped amorphous silicon, doped polycrystalline silicon, a low resistance metal, a refractory metal, an alloy of low resistance metal and refractory metal, a silicide of low resistance metal, and a silicide of refractory metal.

Claim 7

An anti-fuse element according to claim 1, wherein tips of the at least two wiring lines are in proximity to each other and along a straight line, and the tips are covered by the dielectric anti-fuse film under the floating electrode.

Claim 8

An anti-fuse element according to claim 1, wherein tips of the at least two wiring lines are in proximity to each other at the node and are covered by the dielectric anti-fuse film under the floating electrode.

Claim 9

An anti-fuse element according to claim 7, wherein a first capacitance between the tip of a first one of the two wiring lines and the floating electrode equals a second capacitance between the tip of a second one of the two wiring lines and the floating electrode.

Claim 10

An anti-fuse element according to claim 7, wherein the at least two wiring lines are respectively oriented at approximately a right angle to each other.

Claim 11

An anti-fuse element according to claim 7, wherein one of at least two wiring lines is substantially perpendicular to another of the at least two wiring lines.

Claim 12

An anti-fuse element according to claim 1, wherein a tip of one of the at least two wiring lines is proximate to a portion of another of the at least two wiring lines in a region of proximity which is covered by the dielectric anti-fuse film under the floating electrode at the node.

Claim 13

An anti-fuse element according to claim 1, wherein respective portions of the at least two wiring lines are substantially parallel to and in proximity to each other at the node, and are covered by the dielectric anti-fuse film under the floating electrode at the node.

Claim 14

A semiconductor device including a semiconductor substrate, comprising: an insulator layer formed over the semiconductor substrate; two wiring lines formed on the insulator layer, and having predetermined portions in proximity to each other; a dielectric anti-fuse film formed on the two wiring lines at the predetermined portions; a floating electrode formed on the dielectric anti-fuse film to overlap the predetermined portions of the two wiring lines and having no direct contact with a potential source, wherein upon application of a destructive electric potential difference across the wiring lines, the dielectric anti-fuse film breaks down and conductive paths are respectively formed between the floating electrode and each of the two wiring lines; and a functional circuit element selected from a group consisting of a MPU, ROM, RAM, Land a logic connected to one of the two wiring lines.

Claim 15

A semiconductor device including a semiconductor substrate, comprising: an insulator layer formed over the semiconductor substrate; two wiring lines formed on the insulator layer, and having predetermined portions in proximity to each other; a dielectric anti-fuse film formed on the two wiring lines at the predetermined portions; a floating electrode formed on the dielectric anti-fuse film to overlap the predetermined portions of the two wiring lines and having no direct contact with a potential source, wherein upon application of a destructive electric potential difference across the wiring lines, the dielectric anti-fuse film breaks down and conductive paths are respectively formed between the floating electrode and each of the two wiring lines; and a functional circuit element selected from a group consisting of a MPU, ROM, RAM, Land a logic connected to one of the two wiring lines.

Claim 16

A semiconductor memory device including a semiconductor substrate, comprising: an insulator layer formed over the semiconductor substrate; a first and a second wiring line formed on the insulator layer, tips of the first and second wiring lines being in proximity at a node; a dielectric anti-fuse film formed on the tips of the first and second wiring lines at the node; a floating electrode formed on the dielectric anti-fuse film to overlap the tips, and having no direct contact with a potential source,; a word line; a bit line; a source line; and a MOS transistor having a source connected to the source line, a gate connected to the word line, a drain connected to the first wiring line, the second wiring line connected to the bit line, wherein upon application of a destructive electric potential difference across the first and second wiring lines, the dielectric anti-fuse film breaks down and conductive paths are respectively formed between the floating electrode and each of the first and second wiring lines to connect the drain to the bit line.

Claim 17

A semiconductor memory device including a semiconductor substrate, comprising: an insulator layer formed over the semiconductor substrate; a first and a second wiring line formed on the insulator layer, tips of the first and second wiring lines being in proximity at a node; a dielectric anti-fuse film formed on the tips of the first and second wiring lines at the node; a floating electrode formed on the dielectric anti-fuse film to overlap the tips, and having no direct contact with a potential source,; a word line; a bit line; a source line; and a MOS transistor having a source connected to the source line, a gate connected to the word line, a drain connected to the first wiring line, the second wiring line connected to the bit line, wherein upon application of a destructive electric potential difference across the first and second wiring lines, the dielectric anti-fuse film breaks down and conductive paths are respectively formed between the floating electrode and each of the first and second wiring lines to connect the drain to the bit line.

Claim 18

An anti-fuse element formed over a substrate, comprising: an insulator layer formed over the substrate: at least two wiring lines formed on the insulator layer, predetermined portions of the at least two wiring lines being in proximity to each other at a node, and the at least two wiring lines including a first wire line having a predetermined portion and a second wire line having a predetermined portion; a dielectric anti-fuse film formed on the two wiring lines at the node; and a floating electrode formed on the dielectric anti-fuse film to overlap the predetermined portions of the at least two wiring lines at the node which includes a first end and a second end, and has no direct contact with a potential source, wherein upon application of a destructive electric potential difference across the at least two wiring lines, the dielectric anti-fuse film breaks down and conductive paths are respectively formed between the floating electrode and each of the at least two wiring lines; wherein a first capacitor is formed by said first end overlapping the predetermined portion of the first wire line with dielectric anti-fuse film therebetween, and a second capacitor is formed by said second end overlapping the predetermined portion of the second wire line with said dielectric anti-fuse film therebetween, each capacitor having a value, each of the values corresponding to a respective area of overlap.

Claim 19

An anti-fuse element formed over a substrate, comprising: an insulator layer formed over the substrate: at least two wiring lines formed on the insulator layer, predetermined portions of the at least two wiring lines being in proximity to each other at a node, and the at least two wiring lines including a first wire line having a predetermined portion and a second wire line having a predetermined portion; a dielectric anti-fuse film formed on the two wiring lines at the node; and a floating electrode formed on the dielectric anti-fuse film to overlap the predetermined portions of the at least two wiring lines at the node which includes a first end and a second end, and has no direct contact with a potential source, wherein upon application of a destructive electric potential difference across the at least two wiring lines, the dielectric anti-fuse film breaks down and conductive paths are respectively formed between the floating electrode and each of the at least two wiring lines; wherein a first capacitor is formed by said first end overlapping the predetermined portion of the first wire line with dielectric anti-fuse film therebetween, and a second capacitor is formed by said second end overlapping the predetermined portion of the second wire line with said dielectric anti-fuse film therebetween, each capacitor having a value, each of the values corresponding to a respective area of overlap.

Claim 20

The anti-fuse element of claim 15, wherein the respective values of the capacitors are not equal.

Claim 21

The anti-fuse element of claim 15, wherein the respective values of the capacitors are equal.

Claim 22

The anti-fuse element of claim 15, wherein said dielectric anti-fuse film comprises at least one of Si compounds including Si and N, and compounds including Si and O.

Claim 23

The anti-fuse element of claim 18 wherein said dielectric anti-fuse film further comprises at least one of H, F, Cl.

Claim 24

The anti-fuse element of claim 15, wherein said dielectric anti-fusee film comprises a material selected from a group consisting of undoped amorphous silicon, undoped polycrystalline silicon, and an oxide metal film comprising one of Al, Cu, Ti, W, Mo.

Claim 25

The anti-fuse element of claim 15, wherein said floating electrode comprises material selected from a group consisting of doped amorphous silicon, doped polycrystalline silicon, a low resistance metal, a refractory metal, an alloy of low resistance metal anti refractory metal, a silicide of low resistance metal, and a silicide of refractory metal.

Claim 26

The anti-fuse element of claim 15, wherein tips of said at least two wiring lines are in proximity to each other and along a straight line, and said tips are covered by said dielectric anti-fuse film under said floating electrode.

Claim 27

The anti-fuse element of claim 15, wherein tips of said at least two wiring lines are in proximity to each other at said node and are covered by said dielectric anti-fuse film under said floating electrode.

Claim 28

The anti-fuse element of claim 23, wherein a first capacitance between said tip of a first one of said two wiring lines and said floating electrode equals a second in capacitance between said tip of a second one of said two wiring lines and said floating electrode.

Claim 29

The anti-fuse element of claim 23 wherein said at least two wiring lines are respectively oriented at approximately a right angle to each other.

Claim 30

The anti-fuse element of claim 23, wherein one of said at least two wiring lines is substantially perpendicular to another of said at least two wiring lines.

Claim 31

The anti-fuse element of claim 15, wherein a tip of one of said at least two wiring lines is proximate to a portion of another of said at least two wiring lines in a region of proximity which is covered by said dielectric anti-fuse film under said floating electrode.

Claim 32

The anti-fuse element of claim 15, wherein respective portions of said at least two wiring lines are substantially parallel to and in proximity to each other at said node, and are covered by dielectric anti-fuse film under said floating electrode.