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US5624867A Expired / Lapsed US ⏱️ 0.0 years remaining

Low temperature formation of palladium silicided shallow junctions using implant through metal/silicide technology

Assignee: National Science and Technology Council
•
Filing: 1995-05-24
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Granted: 1997-04-29
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Expires: 2015-05-24
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Abstract

Abstract A low temperature process for forming palladium silicided shallow junctions in which ions are implanted into a palladium or a palladium silicide layer over a silicon substrate. The impurities are driven into the silicon substrate during the formation or recrystallization of the palladium silicide layer, and a diffusion region with shallow junction is formed in the substrate.

Inventors

  • 👤 Huang-Chung Cheng
  • 👤 Cheng-Tung Lin
  • 👤 Pei-Fen Chou

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 12:19
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171

Claims Analysis

Total Claims: 22
Claim 1
Independent Claim 114 words
A method for forming a shallow junction in a region of a silicon substrate of a first conductivity type, comprising the steps of: forming a palladium layer directly on said region of said silicon substrate; forming a silicon layer over said palladium layer; implanting impurities of a second conductivity type into said silicon and palladium layers; pre-annealing said silicon substrate and said palladium layer so as to react all of said palladium layer over said region of said substrate to form a silicide layer, performing a selective etch step after said pre-annealing step; and post-annealing said silicon substrate and silicide layer to drive said impurities into said silicon substrate thereby forming said shallow junction.
Claim 2
Independent Claim 114 words
A method for forming a shallow junction in a region of a silicon substrate of a first conductivity type, comprising the steps of: forming a palladium layer directly on said region of said silicon substrate; forming a silicon layer over said palladium layer; implanting impurities of a second conductivity type into said silicon and palladium layers; pre-annealing said silicon substrate and said palladium layer so as to react all of said palladium layer over said region of said substrate to form a silicide layer, performing a selective etch step after said pre-annealing step; and post-annealing said silicon substrate and silicide layer to drive said impurities into said silicon substrate thereby forming said shallow junction.
Claim 3
Dependent Claim 23 words
The method of claim 1, wherein said pre-annealing step is carried out in a nitrogen-containing furnace at a temperature of about 300° C.
Claim 4
Dependent Claim 16 words
The method of claim 2, wherein said pre-annealing step is carried out for about 30 minutes.
Claim 5
Dependent Claim 30 words
The method of claim 1, wherein said post-annealing step is carried out in a nitrogen-containing furnace at a temperature of between 500° C. and 800° C. for about 60 minutes.
Claim 6
Dependent Claim 15 words
The method of claim 1, wherein said palladium layer has a thickness of about 500Å.
Claim 7
Dependent Claim 15 words
The method of claim 1, wherein said silicon layer has a thickness of about 50Å.
Claim 8
Dependent Claim 28 words
The method of claim 1, wherein said silicon substrate of first conductivity type is an N-type silicon substrate and said impurities of second conductivity type are P-type impurities.
Claim 9
Dependent Claim 38 words
The method of claim 7, wherein said implanting step is carried out by implanting BF 2 + ions at an implanting energy of between 70 and 135 KeV and a dosage of about 5×10 15 /cm 2 .
Claim 10
Dependent Claim 23 words
The method of claim 1, wherein said selective etching step is carried out using a solution consisting of iodine and potassium iodide (KI).
Claim 11
Dependent Claim 21 words
The method of claim 1 further comprising the step of depositing an aluminum layer over said silicide layer as contact metallization.
Claim 12
Independent Claim 105 words
A method for forming a shallow junction in a region of a silicon substrate of a first conductivity type, comprising the steps of: forming a palladium layer directly on said region of said silicon substrate; forming a silicon layer over said palladium layer; pre-annealing said silicon substrate and said palladium layer so as to react all of said palladium layer over said region to form a silicide layer; selectively etching unreacted palladium; implanting impurities of a second conductivity type into said silicide layer, after said pre-annealing step; and post-annealing said silicide layer to drive said impurities into said silicon substrate thereby forming said shallow junction.
Claim 13
Independent Claim 105 words
A method for forming a shallow junction in a region of a silicon substrate of a first conductivity type, comprising the steps of: forming a palladium layer directly on said region of said silicon substrate; forming a silicon layer over said palladium layer; pre-annealing said silicon substrate and said palladium layer so as to react all of said palladium layer over said region to form a silicide layer; selectively etching unreacted palladium; implanting impurities of a second conductivity type into said silicide layer, after said pre-annealing step; and post-annealing said silicide layer to drive said impurities into said silicon substrate thereby forming said shallow junction.
Claim 14
Dependent Claim 23 words
The method of claim 11, wherein said pre-annealing step is carried out in a nitrogen-containing furnace at a temperature of about 300° C.
Claim 15
Dependent Claim 16 words
The method of claim 12, wherein said pre-annealing step is carried out for about 30 minutes.
Claim 16
Dependent Claim 29 words
The method of claim 11, wherein said post-annealing step is carried out in a nitrogen-containing furnace at a temperature of between 500° and 800° C. for about 60 minutes.
Claim 17
Dependent Claim 15 words
The method of claim 11, wherein said palladium layer has a thickness of about 500Å.
Claim 18
Dependent Claim 15 words
The method of claim 11, wherein said silicon layer has a thickness of about 50Å.
Claim 19
Dependent Claim 28 words
The method of claim 11, wherein said silicon substrate of first conductivity type is an N-type silicon substrate and said impurities of second conductivity type are P-type impurities.
Claim 20
Dependent Claim 38 words
The method of claim 17, wherein said implanting step is carried out by implanting BF 2 + ions at an implanting energy of between 40 and 120 KeV and a dosage of about 5×10 15 /cm 2 .
Claim 21
Dependent Claim 23 words
The method of claim 11, wherein said selectively etching step is carried out using a solution consisting of iodine and potassium iodide (KI).
Claim 22
Dependent Claim 21 words
The method of claim 11 further comprising the step of depositing an aluminum layer over said silicide layer as contact metallization.

References Cited (Backward Citations)

US5010037A Cited
US5217923A Cited
US5217924A Cited
US5162263A Cited
US5268317A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-04-28 2000-10-28 2001-04-29 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-04-28 2004-10-28 2005-04-29 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-04-28 2008-10-28 2009-04-29 $7700.00 Window Closed / Lapsed

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