Semiconductor integrated device with an improved performance

Claim 2

A semiconductor integrated circuit, comprising: a core for processing first data in units of n bits (n is an integer more than 1); at least one queue of (n×m)-bit width (m>1), for receiving second data having a bit width of (n×m) bits or less from an external memory and storing said second data therein; and a multiplexer for receiving said second data from said at least one queue and selectively outputting n bits out of said second data to said core as said first data.

Claim 3

The semiconductor integrated circuit of claim 1, wherein said at least one queue includes p queues (p is an integer more than 1) serially connected to one another, said p queues constitute a group of queues, and said semiconductor integrated circuit further comprises a queue control portion for transmitting said second data to said multiplexer by sequentially shifting said second data from one of said p queues to the next one.

Claim 4

The semiconductor integrated circuit of claim 2, further comprising a bus of (n×m)-bit width, for transmitting said second data from said external memory to said group of queues.

Claim 5

The semiconductor integrated circuit of claim 3, wherein said second data are variable-length data, and said semiconductor integrated circuit further comprises a selector for outputting said second data to a prescribed memory location of the nearest one of said queues to said bus.

Claim 6

The semiconductor integrated circuit of claim 4, further comprising a cache memory interposed at some midpoint in said bus.

Claim 7

A semiconductor integrated circuit, comprising: (a) a core for processing a first instruction or first data in units of n bits (n is an integer more than 1); (b) a group of instruction queues including (b-1) a first instruction queue of (n×m)-bit width (m>1), for receiving second instruction having a bit width of (n×m) bits or less from an external memory and storing said second instruction therein; and (b-2) an s-th instruction queue (1<s≦p: p is an integer more than 1) of (n×m)-bit width, for receiving said second instruction from an (s-1)-th instruction queue and storing said second instruction therein; said group of instruction queues having serial connection of said first to p-th instruction queues, (c) a group of data queues including (c-1) a first data queue of (n×m)-bit width (m>1), for receiving second data having a bit width of (n×m) bits or less from said external memory and storing said second data therein; and (c-2) a t-th data queue (1<t≦q: q is an integer more than 1) of (n×m)-bit width, for receiving said second data from a (t-1)-th data queue and storing said second data therein; said group of data queues having serial connection of said first to q-th data queues, (d) a queue control portion for sequentially shifting said second instruction and said second data in said group of instruction queues and said group of data queues, respectively; (e) a first multiplexer for receiving said second instruction from said p-th instruction queue and selectively outputting n bits out of said second instruction to said core as said first instruction; and (f) a second multiplexer for receiving said second data from said q-th data queue and selectively outputting n bits out of said second data to said core as said first data.

Claim 8

A semiconductor integrated circuit, comprising: (a) a core for processing a first instruction or first data in units of n bits (n is an integer more than 1); (b) a group of instruction queues including (b-1) a first instruction queue of (n×m)-bit width (m>1), for receiving second instruction having a bit width of (n×m) bits or less from an external memory and storing said second instruction therein; and (b-2) an s-th instruction queue (1<s≦p: p is an integer more than 1) of (n×m)-bit width, for receiving said second instruction from an (s-1)-th instruction queue and storing said second instruction therein; said group of instruction queues having serial connection of said first to p-th instruction queues, (c) a group of data queues including (c-1) a first data queue of (n×m)-bit width (m>1), for receiving second data having a bit width of (n×m) bits or less from said external memory and storing said second data therein; and (c-2) a t-th data queue (1<t≦q: q is an integer more than 1) of (n×m)-bit width, for receiving said second data from a (t-1)-th data queue and storing said second data therein; said group of data queues having serial connection of said first to q-th data queues, (d) a queue control portion for sequentially shifting said second instruction and said second data in said group of instruction queues and said group of data queues, respectively; (e) a first multiplexer for receiving said second instruction from said p-th instruction queue and selectively outputting n bits out of said second instruction to said core as said first instruction; and (f) a second multiplexer for receiving said second data from said q-th data queue and selectively outputting n bits out of said second data to said core as said first data.

Claim 9

The semiconductor integrated circuit of claim 6, wherein said second instruction and said second data are variable-length data, and said semiconductor integrated circuit further comprises (g) a first selector disposed between said group of instruction queues and said external memory, for outputting said second instruction to a prescribed memory location of said first instruction queue; and (h) a second selector disposed between said group of data queues and said external memory, for outputting said second data to a prescribed memory location of said first data queue.

Claim 10

The semiconductor integrated circuit of claim 6, further comprising: (g) an instruction bus connecting said external memory to said first instruction queue, for transmitting said second instruction; and (h) a data bus connecting said external memory to said first data queue, for transmitting said second data.

Claim 11

The semiconductor integrated circuit of claim 8, wherein said external memory is separated into an instruction memory and a data memory, and said instruction bus and said data bus are connected to said instruction memory and said data memory, respectively.

Claim 12

A semiconductor integrated circuit, comprising: (a) a core for processing a first instruction or first data in units of n bits (n is an integer more than 1); (b) a group of instruction queues including (b-1) a first instruction queue of n-bit width, for receiving n bits out of second instruction from an external memory and storing said n bits out of said second instruction therein; and (b-2) an s-th instruction queue (1<s≦p: p is an integer more than 1) of n-bit width, for receiving said n bits out of said second instruction from an (s-1)-th instruction queue and storing said n bits out of said second instruction therein; said group of instruction queues having serial connection of said first to p-th instruction queues, (c) a group of data queues including (c-1) a first data queue of n-bit width, for receiving n bits out of second data from said external memory and storing said n bits out of said second data therein; and (c-2) a t-th data queue (1<t≦q: q is an integer more than 1) of n-bit width, for receiving said n bits out of said second data from a (t-1)-th data queue and storing said n bits out of said second data therein; said group of data queues having serial connection of said first to q-th data queues, (d) a group of common queues of {n×(m-1)}-bit width, for receiving both said second instruction and said second data and storing them therein; (e) a queue control portion for sequentially shifting said second instruction and said second data in said group of instruction queues and said group of data queues, respectively, and in said group of common queues; (f) a first bus of n-bit width connecting said external memory to said first instruction queue and said first data queue, for transmitting said second instruction and said second data; (g) a second bus of {n×(m-1)}-bit width connecting said external memory to said group of common queues, for transmitting said second instruction and said second data; (h) a first multiplexer for receiving said second instruction from both said group of instruction queues and said group of common queues, and selectively outputting said n bits out of said second instruction to said core as said first instruction; and (i) a second multiplexer for receiving said second data from both said group of data queues and said group of common queues, and selectively outputting said n bits out of said second data to said core as said first data.

Claim 13

A semiconductor integrated circuit, comprising: (a) a core for processing a first instruction or first data in units of n bits (n is an integer more than 1); (b) a group of instruction queues including (b-1) a first instruction queue of n-bit width, for receiving n bits out of second instruction from an external memory and storing said n bits out of said second instruction therein; and (b-2) an s-th instruction queue (1<s≦p: p is an integer more than 1) of n-bit width, for receiving said n bits out of said second instruction from an (s-1)-th instruction queue and storing said n bits out of said second instruction therein; said group of instruction queues having serial connection of said first to p-th instruction queues, (c) a group of data queues including (c-1) a first data queue of n-bit width, for receiving n bits out of second data from said external memory and storing said n bits out of said second data therein; and (c-2) a t-th data queue (1<t≦q: q is an integer more than 1) of n-bit width, for receiving said n bits out of said second data from a (t-1)-th data queue and storing said n bits out of said second data therein; said group of data queues having serial connection of said first to q-th data queues, (d) a group of common queues of {n×(m-1)}-bit width, for receiving both said second instruction and said second data and storing them therein; (e) a queue control portion for sequentially shifting said second instruction and said second data in said group of instruction queues and said group of data queues, respectively, and in said group of common queues; (f) a first bus of n-bit width connecting said external memory to said first instruction queue and said first data queue, for transmitting said second instruction and said second data; (g) a second bus of {n×(m-1)}-bit width connecting said external memory to said group of common queues, for transmitting said second instruction and said second data; (h) a first multiplexer for receiving said second instruction from both said group of instruction queues and said group of common queues, and selectively outputting said n bits out of said second instruction to said core as said first instruction; and (i) a second multiplexer for receiving said second data from both said group of data queues and said group of common queues, and selectively outputting said n bits out of said second data to said core as said first data.

Claim 14

The semiconductor integrated circuit of claim 1(), further comprising (j) a cache memory interposed at some midpoint in said second bus.

Claim 15

A semiconductor integrated circuit, comprising: (a) a core for processing a first instruction or first data in units of n bits (n is an integer more than 1); (b) a group of instruction queues including (b-1) a first instruction queue of (n×m)-bit width (m>1), for receiving second instruction having a bit width of (n×m) bits or less from an external memory and storing said second instruction therein; and (b-2) an s-th instruction queue (1<s≦p: p is an integer more than 1) of (n×m)-bit width, for receiving said second instruction from an (s-1)-th instruction queue and storing said second instruction therein; said group of instruction queues having serial connection of said first to p-th instruction queues, (c) a group of data queues including (c-1) a first data queue of n-bit width, for receiving second data of n-bit width from said external memory and storing said second data therein; and (c-2) a t-th data queue (1<t≦q: q is an integer more than 1) of n-bit width, for receiving said second data from a (t-1)-th data queue and storing said second data therein; said group of data queues having serial connection of said first to q-th data queues, (d) a queue control portion for sequentially shifting said second instruction and said second data in said group of instruction queues and said group of data queues, respectively; and (e) a multiplexer for receiving said second instruction from said p-th instruction queue and selectively outputting n bits out of said second instruction to said core as said first instruction, wherein said first data is obtained from said q-th data queue.

Claim 16

A semiconductor integrated circuit, comprising: (a) a core for processing a first instruction or first data in units of n bits (n is an integer more than 1); (b) a group of instruction queues including (b-1) a first instruction queue of (n×m)-bit width (m>1), for receiving second instruction having a bit width of (n×m) bits or less from an external memory and storing said second instruction therein; and (b-2) an s-th instruction queue (1<s≦p: p is an integer more than 1) of (n×m)-bit width, for receiving said second instruction from an (s-1)-th instruction queue and storing said second instruction therein; said group of instruction queues having serial connection of said first to p-th instruction queues, (c) a group of data queues including (c-1) a first data queue of n-bit width, for receiving second data of n-bit width from said external memory and storing said second data therein; and (c-2) a t-th data queue (1<t≦q: q is an integer more than 1) of n-bit width, for receiving said second data from a (t-1)-th data queue and storing said second data therein; said group of data queues having serial connection of said first to q-th data queues, (d) a queue control portion for sequentially shifting said second instruction and said second data in said group of instruction queues and said group of data queues, respectively; and (e) a multiplexer for receiving said second instruction from said p-th instruction queue and selectively outputting n bits out of said second instruction to said core as said first instruction, wherein said first data is obtained from said q-th data queue.

Claim 17

The semiconductor integrated circuit of claim 12, further comprising: (f) an instruction bus connecting said external memory to said first instruction queue, for transmitting said second instruction; and (g) a data bus connecting said external memory to said first data queue, for transmitting said second data.

Claim 18

The semiconductor integrated circuit of claim 13, wherein said external memory is separated into an instruction memory and a data memory, and said instruction bus and said data bus are connected to said instruction memory and said data memory, respectively.

Claim 19

A semiconductor integrated circuit, comprising: (a) a core for processing a first instruction or first data in units of n bits (n is an integer more than 1); (b) a group of instruction queues including (b-1) a first instruction queue of n-bit width, for receiving second instruction of n-bit width from an external memory and storing said second instruction therein; and (b-2) an s-th instruction queue (1<s≦p: p is an integer more than 1) of n-bit width, for receiving said second instruction from an (s-1)-th instruction queue and storing said second instruction therein; said group of instruction queues having serial connection of said first to p-th instruction queues, (c) a group of data queues including (c-1) a first data queue of (n×m)-bit width (m>1), for receiving second data having a bit width of (n×m) bits or less from said external memory and storing said second data therein; and (c-2) a t-th data queue (1<t≦q: q is an integer more than 1) of (n×m)-bit width, for receiving said second data from a (t-1)-th data queue and storing said second data therein; said group of data queues having serial connection of said first to q-th data queues, (d) a queue control portion for sequentially shifting said second instruction and said second data in said group of instruction queues and said group of data queues, respectively; and (e) a multiplexer for receiving said second data from said q-th data queue and selectively outputting n bits out of said second data to said core as said first data, wherein said first instruction is obtained from said p-th instruction queue.

Claim 20

A semiconductor integrated circuit, comprising: (a) a core for processing a first instruction or first data in units of n bits (n is an integer more than 1); (b) a group of instruction queues including (b-1) a first instruction queue of n-bit width, for receiving second instruction of n-bit width from an external memory and storing said second instruction therein; and (b-2) an s-th instruction queue (1<s≦p: p is an integer more than 1) of n-bit width, for receiving said second instruction from an (s-1)-th instruction queue and storing said second instruction therein; said group of instruction queues having serial connection of said first to p-th instruction queues, (c) a group of data queues including (c-1) a first data queue of (n×m)-bit width (m>1), for receiving second data having a bit width of (n×m) bits or less from said external memory and storing said second data therein; and (c-2) a t-th data queue (1<t≦q: q is an integer more than 1) of (n×m)-bit width, for receiving said second data from a (t-1)-th data queue and storing said second data therein; said group of data queues having serial connection of said first to q-th data queues, (d) a queue control portion for sequentially shifting said second instruction and said second data in said group of instruction queues and said group of data queues, respectively; and (e) a multiplexer for receiving said second data from said q-th data queue and selectively outputting n bits out of said second data to said core as said first data, wherein said first instruction is obtained from said p-th instruction queue.

Claim 21

The semiconductor integrated circuit of claim 15, further comprising: (f) an instruction bus connecting said external memory to said first instruction queue, for transmitting said second instruction; and (g) a data bus connecting said external memory to said first data queue, for transmitting said second data.

Claim 22

The semiconductor integrated circuit of claim 16, wherein said external memory is separated into an instruction memory and a data memory, and said instruction bus and said data bus are connected to said instruction memory and said data memory, respectively.

Claim 23

A semiconductor integrated circuit, comprising: (a) a core for processing a first instruction or first data in units of n bits (n is an integer more than 1); (b) a group of instruction queues including (b-1) a first instruction queue of (n×m)-bit width (m>1), for receiving second instruction having a bit width of (n×m) bits or less from an external memory and storing said second instruction therein; and (b-2) an s-th instruction queue (1<s≦p: p is an integer more than 1) of (n×m)-bit width, for receiving said second instruction from an (s-1)-th instruction queue and storing said second instruction therein; said group of instruction queues having serial connection of said first to p-th instruction queues, (c) a group of data queues including (c-1) a first data queue of (n×k)-bit width (k>m), for receiving second data having a bit width of (n×k) bits or less from said external memory and storing said second data therein: and (c-2) a t-th data queue (1<t≦q: q is an integer more than 1) of (n×k)-bit width, for receiving said second data from a (t-1)-th data queue and storing said second data therein; said group of data queues having serial connection of said first to q-th data queues, (d) a queue control portion for sequentially shifting said second instruction and said second data in said group of instruction queues and said group of data queues, respectively; (e) a first multiplexer for receiving said second instruction from said p-th instruction queue and selectively outputting n bits out of said second instruction to said core as said first instruction; and (f) a second multiplexer for receiving said second data from said q-th data queue and selectively outputting n bits out of said second data to said core as said first data.

Claim 24

A semiconductor integrated circuit, comprising: (a) a core for processing a first instruction or first data in units of n bits (n is an integer more than 1); (b) a group of instruction queues including (b-1) a first instruction queue of (n×m)-bit width (m>1), for receiving second instruction having a bit width of (n×m) bits or less from an external memory and storing said second instruction therein; and (b-2) an s-th instruction queue (1<s≦p: p is an integer more than 1) of (n×m)-bit width, for receiving said second instruction from an (s-1)-th instruction queue and storing said second instruction therein; said group of instruction queues having serial connection of said first to p-th instruction queues, (c) a group of data queues including (c-1) a first data queue of (n×k)-bit width (k>m), for receiving second data having a bit width of (n×k) bits or less from said external memory and storing said second data therein: and (c-2) a t-th data queue (1<t≦q: q is an integer more than 1) of (n×k)-bit width, for receiving said second data from a (t-1)-th data queue and storing said second data therein; said group of data queues having serial connection of said first to q-th data queues, (d) a queue control portion for sequentially shifting said second instruction and said second data in said group of instruction queues and said group of data queues, respectively; (e) a first multiplexer for receiving said second instruction from said p-th instruction queue and selectively outputting n bits out of said second instruction to said core as said first instruction; and (f) a second multiplexer for receiving said second data from said q-th data queue and selectively outputting n bits out of said second data to said core as said first data.

Claim 25

The semiconductor integrated circuit of claim 18, further comprising: (g) an instruction bus connecting said external memory to said first instruction queue, for transmitting said second instruction; and (h) a data bus connecting said external memory to said first data queue, for transmitting said second data.

Claim 26

The semiconductor integrated circuit of claim 19, wherein said external memory is separated into an instruction memory and a data memory, and said instruction bus and said data bus are connected to said instruction memory and said data memory, respectively.

Claim 27

The semiconductor integrated circuit of claim 3, further comprising an aligner interposed at some midpoint in said bus.

Claim 28

The semiconductor integrated circuit of claim 8, further comprising an aligner interposed at some midpoint in at least one of said instruction bus and said data bus.

Claim 29

The semiconductor integrated circuit of claim 13, further comprising an aligner interposed at some midpoint in at least one of said instruction bus and said data bus.

Claim 30

The semiconductor integrated circuit of claim 16, further comprising an aligner interposed at some midpoint in at least one of said instruction bus and said data bus.

Claim 31

The semiconductor integrated circuit of claim 19, further comprising an aligner interposed at some midpoint in at least one of said instruction bus and said data bus.