Patent US5621312A successfully refreshed from Google Patents.
US5621312A
Expired / Lapsed
US
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Method and apparatus for checking the integrity of a device tester-handler setup
Assignee: Altera Corp
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Filing: 1995-07-05
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Granted: 1997-04-15
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Expires: 2015-07-05
Abstract
Abstract A method and apparatus for checking the integrity of a device tester used in the manufacture of semiconductor devices. A device tester is used to exercise different aspects of a semiconductor device. The tester is programmed with appropriate control software that fully tests the electrical and functional characteristics of the semiconductor device.
Inventors
- 👤 Alan Achor
- 👤 Eric F. H. Chun
- 👤 Ernest Allen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:38
CPC Classifications
G; G01; G01R; G01R35/00; G01R35/005
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
87 words
A configuration for verifying a semiconductor device tester-handler setup comprising: a device tester including signal generation circuitry and measurement circuitry for performing electrical or functional tests on a device under test; a loadboard coupled to said device tester for holding said device under test; a device handler coupled to said loadboard for holding a plurality of semiconductor devices, said device handler loading said device under test onto said loadboard; and a direct electrical connection between said signal generation circuitry and said measurement circuitry of said device tester.
Claim 2
Dependent Claim
87 words
A configuration for verifying a semiconductor device tester-handler setup comprising: a device tester including signal generation circuitry and measurement circuitry for performing electrical or functional tests on a device under test; a loadboard coupled to said device tester for holding said device under test; a device handler coupled to said loadboard for holding a plurality of semiconductor devices, said device handler loading said device under test onto said loadboard; and a direct electrical connection between said signal generation circuitry and said measurement circuitry of said device tester.
Claim 3
Dependent Claim
27 words
The configuration of claim 1 wherein said direct electrical connection further comprises an ohmic connection made with a wire inside a device package without logic cells therein.
Claim 4
Dependent Claim
15 words
The configuration of claim 1 wherein said direct electrical connection further comprises a shorting block.
Claim 5
Dependent Claim
30 words
The configuration of claim 3 wherein said shorting block further comprises a device package having a plurality of signal pins, wherein adjacent signal pins are directly coupled to each other.
Claim 6
Dependent Claim
30 words
The configuration of claim 3 wherein said shorting block further comprises a device package having a plurality of signal pins, wherein all signal pins are directly coupled to each other.
Claim 7
Dependent Claim
35 words
The configuration of claim 3 wherein said shorting block further comprises a device package having a plurality of signal pins, wherein a first selected signal pin is directly coupled to a second selected signal pin.
Claim 8
Dependent Claim
47 words
The configuration of claim 3 wherein said shorting block further comprises a device package having a plurality of signal pins, a temperature sensing device coupling a first selected signal pin to a second selected signal pin, said temperature sensing device measuring an operating temperature of the configuration.
Claim 9
Independent Claim
99 words
A method of verifying integrity of a semiconductor device tester-handler setup comprising the steps of: providing a device tester including signal generation circuitry and measurement circuitry for performing electrical or functional tests on a device under test; providing a loadboard coupled to said device tester for holding said device under test in a socket; providing a device handler coupled to said loadboard for holding a plurality of semiconductor devices, said device handler loading said device under test into said socket; and establishing a direct electrical connection between said signal generation circuitry and said measurement circuitry of said device tester.
Claim 10
Independent Claim
99 words
A method of verifying integrity of a semiconductor device tester-handler setup comprising the steps of: providing a device tester including signal generation circuitry and measurement circuitry for performing electrical or functional tests on a device under test; providing a loadboard coupled to said device tester for holding said device under test in a socket; providing a device handler coupled to said loadboard for holding a plurality of semiconductor devices, said device handler loading said device under test into said socket; and establishing a direct electrical connection between said signal generation circuitry and said measurement circuitry of said device tester.
Claim 11
Dependent Claim
39 words
The method of claim 8 further comprising the steps of: measuring timing characteristics of said device tester through said direct electrical connection; and adapting said timing characteristics of said device tester in accordance with results of said measuring step.
Claim 12
Dependent Claim
35 words
The method of claim 8 wherein said step of establishing a direct electrical connection further comprises the step of establishing an ohmic connection made with a wire inside a device package without logic cells therein.
Claim 13
Dependent Claim
26 words
The method of claim 8 wherein said step of establishing a direct electrical connection further comprises the step of placing a shorting block in said socket.
Claim 14
Dependent Claim
44 words
The method of claim 9 wherein said step of placing a shorting block in said socket further comprises the step of placing a device package in said socket having a plurality of signal pins wherein adjacent signal pins are directly coupled to each other.
Claim 15
Dependent Claim
44 words
The method of claim 9 wherein said step of placing a shorting block in said socket further comprises the step of placing a device package in said socket having a plurality of signal pins wherein all signal pins are directly coupled to each other.
Claim 16
Dependent Claim
49 words
The method of claim 9 wherein said step of placing a shorting block in said socket further comprises the step of placing a device package in said socket having a plurality of signal pins wherein a first selected signal pin is directly coupled to a second selected signal pin.
Claim 17
Dependent Claim
62 words
The method of claim 9 wherein said step of placing a shorting block in said socket further comprises the step of placing a device package in said socket having a plurality of signal pins wherein a temperature sensing device couples a first selected signal pin to a second selected signal pin, said temperature sensing device measuring an operating temperature of the configuration.
Claim 18
Independent Claim
176 words
A method of manufacturing an integrated circuit chip comprising the steps of: preparing and fabricating a plurality of electrical circuits on a semiconductor wafer; testing the semiconductor wafer to identify functioning circuits in said plurality of electrical circuits; separating said semiconductor wafer into individual chip die to isolate said functioning circuits; assembling each of individual chip die containing said functioning circuits into a separate device package; verifying integrity of a configuration for a device tester, said verifying step comprising the steps of: providing said device tester including signal generation circuitry and measurement circuitry for performing electrical or functional tests on a device under test; providing a loadboard coupled to said device tester for holding said device under test in a socket; providing a device handler coupled to said loadboard for holding a plurality of semiconductor devices, said device handler loading said device under test into said socket; and establishing a direct electrical connection between said signal generation circuitry and said measurement circuitry of said device tester; and testing said separate device package with said device tester.
Claim 19
Independent Claim
176 words
A method of manufacturing an integrated circuit chip comprising the steps of: preparing and fabricating a plurality of electrical circuits on a semiconductor wafer; testing the semiconductor wafer to identify functioning circuits in said plurality of electrical circuits; separating said semiconductor wafer into individual chip die to isolate said functioning circuits; assembling each of individual chip die containing said functioning circuits into a separate device package; verifying integrity of a configuration for a device tester, said verifying step comprising the steps of: providing said device tester including signal generation circuitry and measurement circuitry for performing electrical or functional tests on a device under test; providing a loadboard coupled to said device tester for holding said device under test in a socket; providing a device handler coupled to said loadboard for holding a plurality of semiconductor devices, said device handler loading said device under test into said socket; and establishing a direct electrical connection between said signal generation circuitry and said measurement circuitry of said device tester; and testing said separate device package with said device tester.
Claim 20
Dependent Claim
45 words
The method of claim 16 wherein said step of verifying integrity further comprising the steps of: measuring timing characteristics of said device tester through said direct electrical connection; and adapting said timing characteristics of said device tester in accordance with results of said measuring step.
Claim 21
Dependent Claim
35 words
The method of claim 16 wherein said step of establishing a direct electrical connection further comprises the step of establishing an ohmic connection made with a wire inside a device package without logic cells therein.
Claim 22
Dependent Claim
26 words
The method of claim 16 wherein said step of establishing a direct electrical connection further comprises the step of placing a shorting block in said socket.
Claim 23
Dependent Claim
44 words
The method of claim 19 wherein said step of placing a shorting block in said socket further comprises the step of placing a device package in said socket having a plurality of signal pins wherein adjacent signal pins are directly coupled to each other.
Claim 24
Dependent Claim
44 words
The method of claim 19 wherein said step of placing a shorting block in said socket further comprises the step of placing a device package in said socket having a plurality of signal pins wherein all signal pins are directly coupled to each other.
Claim 25
Dependent Claim
49 words
The method of claim 19 wherein said step of placing a shorting block in said socket further comprises the step of placing a device package in said socket having a plurality of signal pins wherein a first selected signal pin is directly coupled to a second selected signal pin.
Claim 26
Dependent Claim
62 words
The method of claim 19 wherein said step of placing a shorting block in said socket further comprises the step of placing a device package in said socket having a plurality of signal pins wherein a temperature sensing device couples a first selected signal pin to a second selected signal pin, said temperature sensing device measuring an operating temperature of the configuration.
Claim 27
Dependent Claim
14 words
A system comprising a integrated circuit manufactured by the method recited in claim 16.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-14 | 2000-10-14 | 2001-04-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-14 | 2004-10-14 | 2005-04-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-14 | 2008-10-14 | 2009-04-15 | $7700.00 | Window Closed / Lapsed |