Patent US5619791A successfully refreshed from Google Patents.
US5619791A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for fabricating highly conductive vias
Assignee: Nokia of America Corp
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Filing: 1995-04-28
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Granted: 1997-04-15
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Expires: 2015-04-28
Abstract
Abstract The thickness uniformity of a plated metal layer inside a via hole can be enhanced by intersecting a conductive via with an insulating aperture before plating. The new via configuration improves the mass transfer of the plating. It is believed that the apertures lower the local solution ohmic resistance near the via holes. The method can be applied to the manufacture of a wide variety of circuit boards.
Inventors
- 👤 Vincent G. Lambrecht, Jr.
- 👤 Henry H. Law
- 👤 Apurba Roy
- 👤 John Thomson, Jr.
- 👤 Te-Sung Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 06:49
CPC Classifications
H; H01; H01F; H01F17/00; H01F17/0006; H01F17/0033; H01F41/00; H01F41/02; H01F41/04; H01F41/041; H01F41/046; H05; H05K; H05K1/00; H05K1/02; H05K1/11; H05K1/115; H05K3/00; H05K3/40; H05K3/403; H10; H10W; H10W70/00; H10W70/01; H10W70/05; H10W70/095; H01F2017/004; H05K1/03; H05K1/0306; H05K1/09; H05K1/092; H05K2201/00; H05K2201/09; H05K2201/09209; H05K2201/095; H05K2201/09645; H05K2201/09818; H05K2201/09854; H05K2203/00; H05K2203/14; H05K2203/1476; H05K3/0011; H05K3/0044; H05K3/005; H05K3/22; H05K3/24; H05K3/245; H05K3/4038; H05K3/4053; H05K3/4061; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49155; Y10T29/49165
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
96 words
A method for making conductive vias in an insulating substrate comprising the steps of: providing an insulating substrate having a pair of major surfaces; forming a plurality of via through-holes in said substrate between said major surfaces; applying a first coating of conductive material to said substrate within said via holes; forming one or more apertures in said substrate intersecting said conductively coated via holes so that the peripheries of the resulting composite apertures include both conductively coated via portions and insulating portions; and plating said conductively coated via portions with a second layer of conductor.
Claim 2
Independent Claim
96 words
A method for making conductive vias in an insulating substrate comprising the steps of: providing an insulating substrate having a pair of major surfaces; forming a plurality of via through-holes in said substrate between said major surfaces; applying a first coating of conductive material to said substrate within said via holes; forming one or more apertures in said substrate intersecting said conductively coated via holes so that the peripheries of the resulting composite apertures include both conductively coated via portions and insulating portions; and plating said conductively coated via portions with a second layer of conductor.
Claim 3
Dependent Claim
27 words
The method of claim 1 wherein said substrate is sintered ceramic and said via holes and said apertures are made by punching the ceramic prior to sintering.
Claim 4
Dependent Claim
22 words
The method of claim 1 wherein said substrate is printed circuit board and said via holes and apertures are made by drilling.
Claim 5
Dependent Claim
11 words
The method of claim 1 wherein said via holes are rectangular.
Claim 6
Dependent Claim
38 words
The method of claim 1 wherein said via holes are rectangular; said apertures are rectangular; and at least one aperture edge intersects a plurality of vias to form a crenelated edge including a plurality of conductive via edges.
Claim 7
Dependent Claim
13 words
The method of claim 1 wherein said second layer of conductor is copper.
References Cited (Backward Citations)
US3349480A
Cited
JPS5439322A
Cited
JPS56120058A
Cited
JPS56152447A
Cited
US4522671A
Cited
US4543715A
Cited
JPS59212335A
Cited
US4775465A
Cited
JPS62254879A
Cited
JPS63297083A
Cited
JPH01297487A
Cited
JPH02232986A
Cited
US5029043A
Cited
US5136120A
Cited
EP0467698A2
Cited
GB2252208A
Cited
US5161098A
Cited
US5239744A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-14 | 2000-10-14 | 2001-04-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-14 | 2004-10-14 | 2005-04-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-14 | 2008-10-14 | 2009-04-15 | $7700.00 | Window Closed / Lapsed |