Apparatus and method for supporting multiple interrupt protocols with unequal number of interrupt request signals

Claim 2

A peripheral device operable with an interrupt controller in a computer system capable of supporting a first interrupt type responsive to a first bus protocol or a second interrupt type responsive to a second bus protocol, wherein said first or said second interrupt type comprise a first and a second plurality of interrupt request signals respectively, said peripheral device comprising a converter circuit coupled to a signal generation circuit for receiving a first plurality of interrupt request signals during a first plurality of clock cycles, and generating a second plurality of interrupt request signals over a third set of external pins during a second plurality of clock cycles to an interrupt controller; and wherein said signal generation circuit and said converter circuit are both driven by a common system clock signal, said converter circuit comprising: a plurality of tri-state devices, each of said devices being coupled to receive an enable bit and an input bit of a corresponding interrupt request signal, each of said plurality of tri-state devices outputting said input bit on a corresponding pin in said third set of external pins if said enable bit is set to a first value, and driving said corresponding pin to a high-impedance state if said enable bit is set to a second value; and a plurality of latches coupled to a second logic circuit to receive and store a first set of data bits, each of said plurality of latches being coupled to each of said plurality of tri-state devices, and wherein said first set of bits comprise said input bits and said enable bits.

Claim 3

The peripheral device of claim 1 wherein said second set of external pins comprise a first pin and wherein said second logic circuit serially transmits said first set of bits over to said first pin.

Claim 4

The peripheral device of claim 2 wherein at least one of said second plurality of interrupt request signals provided to said interrupt controller comprises a pulse signal.

Claim 5

The peripheral device of claim 3 wherein at least one of said second plurality of interrupt request signals provided to said interrupt controller comprises a level signal.

Claim 6

The peripheral device of claim 4 wherein said second logic circuit comprises: a core logic circuit for generating said first set of data bits; and a parallel-to-serial circuit for receiving said first set of data bits, and serially transferring said first set of data bits over said first pin.

Claim 7

The peripheral device of claim 5 further comprising an external select pin for selectively disabling either said first logic circuit or said second logic circuit from generating said first plurality and said second plurality of interrupt signal requests respectively upon receipt of a select signal over said select pin during initialization of said device.

Claim 8

A peripheral device operable with an interrupt controller in a computer system capable of supporting a first interrupt type responsive to a first bus protocol or a second interrupt type responsive to a second bus protocol, wherein said first or said second interrupt type comprise a first and a second plurality of interrupt request signals respectively, said peripheral device comprising: a first integrated circuit for generating said first plurality of interrupt request signals responsive to said first interrupt type, and providing said first plurality of interrupt request signals over a first set of external pins to said interrupt controller; a second integrated circuit for generating said second plurality of interrupt request signals responsive to said second interrupt type, and wherein a first set of bits representing said second plurality of interrupt request signals is transmitted over a second set of external pins during a first plurality of clock cycles to said interrupt controller; and a converter circuit coupled to said first integrated circuit or said second integrated circuit for receiving said first set of bits during said first plurality of clock cycles, and generating said second plurality of interrupt request signals responsive to said first set of bits over a third set of pins during a second plurality of clock cycles to said interrupt controller, said converter circuit comprising: a plurality of tri-state devices, each of said tri-state devices coupled to receive an enable bit and an input bit, wherein said first set of bits comprise said enable bits and said input bits, wherein each of said tri-state device drive an output signal line to a high-impedance state if a corresponding enable bit is set to a first value and drives said output signal line to a value corresponding to said input bit if the enable bit is set to a second value; and a plurality of flip-flops coupled to said plurality of tri-state devices for receiving said first set of bits, and providing said enable bits and said input bits to said tri-state devices.

Claim 9

A peripheral device operable with an interrupt controller in a computer system capable of supporting a first interrupt type responsive to a first bus protocol or a second interrupt type responsive to a second bus protocol, wherein said first or said second interrupt type comprise a first and a second plurality of interrupt request signals respectively, said peripheral device comprising: a first integrated circuit for generating said first plurality of interrupt request signals responsive to said first interrupt type, and providing said first plurality of interrupt request signals over a first set of external pins to said interrupt controller; a second integrated circuit for generating said second plurality of interrupt request signals responsive to said second interrupt type, and wherein a first set of bits representing said second plurality of interrupt request signals is transmitted over a second set of external pins during a first plurality of clock cycles to said interrupt controller; and a converter circuit coupled to said first integrated circuit or said second integrated circuit for receiving said first set of bits during said first plurality of clock cycles, and generating said second plurality of interrupt request signals responsive to said first set of bits over a third set of pins during a second plurality of clock cycles to said interrupt controller, said converter circuit comprising: a plurality of tri-state devices, each of said tri-state devices coupled to receive an enable bit and an input bit, wherein said first set of bits comprise said enable bits and said input bits, wherein each of said tri-state device drive an output signal line to a high-impedance state if a corresponding enable bit is set to a first value and drives said output signal line to a value corresponding to said input bit if the enable bit is set to a second value; and a plurality of flip-flops coupled to said plurality of tri-state devices for receiving said first set of bits, and providing said enable bits and said input bits to said tri-state devices.

Claim 10

The peripheral device of claim 7 wherein said second chip generates a level signal on one of said interrupt request signal lines in response to said first set of bits generated by said first integrated circuit.

Claim 11

The peripheral device of claim 8 wherein said first integrated circuit comprises: a core logic for generating said first set of data bits; and a parallel-to-serial circuit for receiving said first set of data bits, and transferring one said first set of bits serially over said first external pin to said second integrated circuit.

Claim 12

A computer system comprising: a peripheral device operable in a first interrupt type or a second interrupt type, said first interrupt protocol comprising a first plurality of interrupt request signals and said second interrupt protocol comprising a second plurality of interrupt request signals, and wherein said first set of interrupt request signals comprise a lesser number of interrupt request signals than said second set of interrupt request signals, said peripheral device comprising: a first logic circuit for generating said first plurality of interrupt request signals, and providing said first plurality of interrupt request signals over a first set of external pins; a second logic circuit for generating a first set of bits corresponding to said second interrupt protocol, and sending said first set of bits over a second set of pins during a plurality of clock cycles; and a converter circuit coupled to said second logic circuit for receiving said first set of bits during said plurality of clock cycles, and generating said second plurality of interrupt request signals responsive to said first set of bits over a third set of pins to an interrupt controller, said interrupt controller coupled to said converter circuit for receiving said interrupt request signals, and generating an indication signal indicative of the presence of an interrupt request signal on one of said interrupt request lines; and a processor coupled said interrupt controller for processing said interrupt request signals in response to said indication signal, said converter circuit comprising: a plurality of tri-state devices, each of said devices coupled to receive an enable bit and an input bit of a corresponding interrupt request signal, each of said tri-state devices outputting said input bit on a corresponding pin in said third set of pins if said enable bit is set to a first value, and driving said corresponding pin to a high-impedance state if said enable bit is set to a second value; and a plurality of latches the inputs of which are coupled to said second logic circuit to receive said first set of bits, each of said latches storing each of said first set of bits, the outputs of each of said plurality of latches coupled to each of said tri-state devices wherein said first set of bits comprise said input bits and said enable bits.

Claim 13

A computer system comprising: a peripheral device operable in a first interrupt type or a second interrupt type, said first interrupt protocol comprising a first plurality of interrupt request signals and said second interrupt protocol comprising a second plurality of interrupt request signals, and wherein said first set of interrupt request signals comprise a lesser number of interrupt request signals than said second set of interrupt request signals, said peripheral device comprising: a first logic circuit for generating said first plurality of interrupt request signals, and providing said first plurality of interrupt request signals over a first set of external pins; a second logic circuit for generating a first set of bits corresponding to said second interrupt protocol, and sending said first set of bits over a second set of pins during a plurality of clock cycles; and a converter circuit coupled to said second logic circuit for receiving said first set of bits during said plurality of clock cycles, and generating said second plurality of interrupt request signals responsive to said first set of bits over a third set of pins to an interrupt controller, said interrupt controller coupled to said converter circuit for receiving said interrupt request signals, and generating an indication signal indicative of the presence of an interrupt request signal on one of said interrupt request lines; and a processor coupled said interrupt controller for processing said interrupt request signals in response to said indication signal, said converter circuit comprising: a plurality of tri-state devices, each of said devices coupled to receive an enable bit and an input bit of a corresponding interrupt request signal, each of said tri-state devices outputting said input bit on a corresponding pin in said third set of pins if said enable bit is set to a first value, and driving said corresponding pin to a high-impedance state if said enable bit is set to a second value; and a plurality of latches the inputs of which are coupled to said second logic circuit to receive said first set of bits, each of said latches storing each of said first set of bits, the outputs of each of said plurality of latches coupled to each of said tri-state devices wherein said first set of bits comprise said input bits and said enable bits.

Claim 14

The peripheral device of claim 10 wherein at least one of said second set of interrupt request signals provided to said interrupt controller comprises a pulse signal.

Claim 15

The peripheral device of claim 11 wherein at least one of said second set of interrupt request signals provided to said interrupt controller comprises a level signal.

Claim 16

The peripheral device of claim 12 wherein said second logic circuit comprises: a core logic circuit for generating said first set of bits; and a parallel-to-serial circuit for receiving said first set of data bits, and transferring said first set of data bits over said first pin.

Claim 17

The peripheral device of claim 13 further comprising a select pin, wherein said first logic circuit is disabled from generating said first set of interrupt signal requests upon receipt of a select signal over said select pin.

Claim 18

The peripheral device of claim 14 wherein the second interrupt type is an ISA interrupt protocol.

Claim 19

The peripheral device of claim 15 wherein the first interrupt type is a PCI interrupt protocol.