Method and interface adapter for interfacing an ISA board to an MCA system by the issuance of an ILLINI-CDCHRDY signal from the interface adapter

Claim 1

A method of interfacing an Industry Standards Architecture board (hereinafter referred to as an ISA board) to a Micro Channel System (hereinafter referred to as an MCA system) to enable a first signal (IOCHRDY) from the ISA board to initiate data transfer to said MCA system in response to said first signal (Cmd -- Act -- ) from said MCA system, said interfacing solving a timing problem in which the first signal (IOCHRDY) from the ISA board and the first signal Cmd -- Act -- from said MCA system occur at the same time, said method comprising the steps of: (a) issuing a first signal (ILLINI -- CDCHRDY) from an interface located between said ISA board and said MCA system which responds to a second signal (Status) from said MCA system; (b) keeping said first signal (ILLINI -- CDCHRDY) from said interface at an active level during a time when said first signal (Cmd -- Act -- ) from said MCA system is active, with said first signal (ILLINI -- CDCHRDY) from said interface occurring after said second signal (Status) from said MCA system but before said first signal (Cmd -- Act -- ) from said MCA system; and (c) keeping said first signal (ILLINI -- CDCHRDY) from said interface at an active level until said first signal (IOCHRDY) from said ISA board becomes active to initiate the data transfer to said MCA system.

Claim 2

A method of interfacing an Industry Standards Architecture board (hereinafter referred to as an ISA board) to a Micro Channel System (hereinafter referred to as an MCA system) to enable a first signal (IOCHRDY) from the ISA board to initiate data transfer to said MCA system in response to said first signal (Cmd -- Act -- ) from said MCA system, said interfacing solving a timing problem in which the first signal (IOCHRDY) from the ISA board and the first signal Cmd -- Act -- from said MCA system occur at the same time, said method comprising the steps of: (a) issuing a first signal (ILLINI -- CDCHRDY) from an interface located between said ISA board and said MCA system which responds to a second signal (Status) from said MCA system; (b) keeping said first signal (ILLINI -- CDCHRDY) from said interface at an active level during a time when said first signal (Cmd -- Act -- ) from said MCA system is active, with said first signal (ILLINI -- CDCHRDY) from said interface occurring after said second signal (Status) from said MCA system but before said first signal (Cmd -- Act -- ) from said MCA system; and (c) keeping said first signal (ILLINI -- CDCHRDY) from said interface at an active level until said first signal (IOCHRDY) from said ISA board becomes active to initiate the data transfer to said MCA system.

Claim 6

A system comprising: a Micro Channel System (hereinafter referred to as an MCA system) which operates according to an MCA specification which requires that a CDCHRDY signal coming from an adapter board become active after a Status signal from the MCA system becomes active but before a Cmd -- Act -- signal from the MCA system becomes active; an Industrial Standards Architecture board (hereinafter referred to as an ISA board) in which the CDCHRDY signal is not active before the Cmd -- Act -- signal from the MCA system is active; and an interface having logic to: (a) issue a first signal (ILLINI -- CDCHRDY) which responds to the Status signal from said MCA system; (b) keep said first signal (ILLINI -- CDCHRDY) at an active level during a time when the Cmd -- Act -- signal from the MCA system becomes active; and (c) keep said first signal (ILLINI -- CDCHRDY) at an active level and to combine said first signal (ILLINI -- CDCHRDY) with the IOCHRDY signal coming from the ISA board and to present one CDCHRDY signal to said MCA system for an Asynchronous Extended Slot.

Claim 7

A system comprising: a Micro Channel System (hereinafter referred to as an MCA system) which operates according to an MCA specification which requires that a CDCHRDY signal coming from an adapter board become active after a Status signal from the MCA system becomes active but before a Cmd -- Act -- signal from the MCA system becomes active; an Industrial Standards Architecture board (hereinafter referred to as an ISA board) in which the CDCHRDY signal is not active before the Cmd -- Act -- signal from the MCA system is active; and an interface having logic to: (a) issue a first signal (ILLINI -- CDCHRDY) which responds to the Status signal from said MCA system; (b) keep said first signal (ILLINI -- CDCHRDY) at an active level during a time when the Cmd -- Act -- signal from the MCA system becomes active; and (c) keep said first signal (ILLINI -- CDCHRDY) at an active level and to combine said first signal (ILLINI -- CDCHRDY) with the IOCHRDY signal coming from the ISA board and to present one CDCHRDY signal to said MCA system for an Asynchronous Extended Slot.