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US5619662A
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Memory reference tagging
Assignee: Hewlett Packard Development Co LP
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Filing: 1994-08-12
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Granted: 1997-04-08
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Expires: 2014-08-12
Abstract
Abstract A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions, to reorder the issuance of the set of instructions from the instruction processor. The mapped register operand fields are associated with the corresponding instructions of the reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.
Inventors
- 👤 Simon C. Steely, Jr.
- 👤 David J. Sager
- 👤 David B. Fite, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 22:13
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3861; G06F9/3863; G06F9/30098; G06F9/3012; G06F9/30141; G06F9/32; G06F9/322; G06F9/3802; G06F9/3824; G06F9/3826; G06F9/3834; G06F9/3836; G06F9/3838; G06F9/384; G06F9/3842; G06F9/3848; G06F9/3854; G06F9/3856; G06F9/3858
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
143 words
Apparatus, comprising: a write buffer cache responsive to memory reference instructions, comprising: means for checking for collisions between memory reference instructions; means, responsive to said collision checking means, for providing a tag for each one of a plurality of memory reference instructions; means, addressed by an instruction address of said plurality of memory reference instructions, for storing said tags for each of said plurality of said memory reference instructions by an instruction address; means for ordering execution of a first, fetched memory reference instruction after a second, fetched memory reference instruction, if a tag provided from said tag store means and associated with said first instruction is different than a tag provided from said tag store means and associated with said second instruction and for maintaining said order of first and second instructions if tags associated with each of said instructions are equal.
Claim 2
Dependent Claim
143 words
Apparatus, comprising: a write buffer cache responsive to memory reference instructions, comprising: means for checking for collisions between memory reference instructions; means, responsive to said collision checking means, for providing a tag for each one of a plurality of memory reference instructions; means, addressed by an instruction address of said plurality of memory reference instructions, for storing said tags for each of said plurality of said memory reference instructions by an instruction address; means for ordering execution of a first, fetched memory reference instruction after a second, fetched memory reference instruction, if a tag provided from said tag store means and associated with said first instruction is different than a tag provided from said tag store means and associated with said second instruction and for maintaining said order of first and second instructions if tags associated with each of said instructions are equal.
Claim 3
Dependent Claim
54 words
The apparatus as recited in claim 1 wherein said means for providing tags comprises: means for determining if a first memory location address addressed by a load instruction and a second memory location address addressed by a store instruction of a load-store pair of memory reference instructions address the same address location in memory.
Claim 4
Dependent Claim
41 words
The apparatus as recited in claim 2 wherein said means for providing tags further comprises: means for storing a portion of the address of the address location in memory and for providing said address portion to said memory tag store means.
Claim 5
Dependent Claim
24 words
The apparatus as recited in claim 3 wherein said address portion is a group of 2 to 5 lower order bits of the address.
Claim 6
Dependent Claim
54 words
The apparatus as recited in claim 4 wherein said means for providing tags further comprises: means for counting a number of instances that said store-load pair have the same address and can not be reordered, and for using a count value of said instances as tag bits associated with each of said store-load instructions.
Claim 7
Dependent Claim
48 words
The apparatus as recited in claim 5 wherein said means for providing tags further comprises: means for providing a bit associated with a first memory reference instruction, said bit if set indicating that preceeding and subsequent memory reference instructions cannot be reorder around said first memory reference instruction.
Claim 8
Dependent Claim
37 words
The apparatus as recited in claim 6 wherein said means for providing a tag further comprises: means for turning off reordering of instructions for a predetermined number of instructions when an executing instruction steam enters a subroutine.
Claim 9
Dependent Claim
111 words
Apparatus, comprising: means for providing a tag for each one of a plurality of memory reference instructions; means, addressed by an instruction address of said plurality of memory reference instructions, for storing said tags for said memory reference instructions; means for ordering execution of a first, fetched memory reference instruction after a second, fetched memory reference instruction if a first tag provided from said tag store means and associated with said first instruction is different than a second tag provided from said tag store means and associated with said second instruction and for maintaining said order of first and second instructions if tags associated with each of said instructions are equal.
Claim 10
Dependent Claim
111 words
Apparatus, comprising: means for providing a tag for each one of a plurality of memory reference instructions; means, addressed by an instruction address of said plurality of memory reference instructions, for storing said tags for said memory reference instructions; means for ordering execution of a first, fetched memory reference instruction after a second, fetched memory reference instruction if a first tag provided from said tag store means and associated with said first instruction is different than a second tag provided from said tag store means and associated with said second instruction and for maintaining said order of first and second instructions if tags associated with each of said instructions are equal.
Claim 11
Dependent Claim
55 words
The apparatus as recited in claim 8 wherein said means for providing tags comprises: means for determining if a first memory location address addressed by a load instruction and a second memory location address addressed by a store instruction of a load-store pair of memory reference instructions address the same address location in a memory.
Claim 12
Dependent Claim
49 words
The apparatus as recited in claim 9 wherein said means for providing tags further comprises: means for storing a portion of the address of the address location in memory and for providing said address portion to said memory tag store means as a tag for said memory reference instruction.
Claim 13
Dependent Claim
24 words
The apparatus as recited in claim 10 wherein said address portion is a group of 2 to 5 lower order bits of the address.
Claim 14
Dependent Claim
48 words
The apparatus as recited in claim 11 wherein said means for providing tags further comprises: means for providing a bit associated with a first memory reference instruction, said bit if set indicating that preceding and subsequent memory reference instructions cannot be reordered around said first memory reference instruction.
Claim 15
Dependent Claim
51 words
The apparatus as recited in claim 9 wherein said means for providing tags further comprises: means for counting a number of instances that said store-load pair have the same address and can not be reordered, and for using a count value as tag bits associated with each of said store-load instructions.
Claim 16
Dependent Claim
72 words
Apparatus, comprising: means for providing a tag for a plurality of memory reference instructions, said memory reference instructions provided in a first order of issuance; means, addressed by an instruction address of said plurality of memory reference instructions, for storing said tags for said memory reference instructions; means for reordering issuance of said memory reference instructions to a second different order in accordance with the tags associated with said memory reference instructions.
Claim 17
Dependent Claim
72 words
Apparatus, comprising: means for providing a tag for a plurality of memory reference instructions, said memory reference instructions provided in a first order of issuance; means, addressed by an instruction address of said plurality of memory reference instructions, for storing said tags for said memory reference instructions; means for reordering issuance of said memory reference instructions to a second different order in accordance with the tags associated with said memory reference instructions.
Claim 18
Dependent Claim
32 words
The apparatus of claim 1 wherein said means for reordering comprises: means for maintaining the first order of first and second instructions if tags associated with each of said instructions are equal.
Claim 19
Dependent Claim
64 words
The apparatus of claim 15 wherein said means for reordering further comprises: means for ordering execution of the first, fetched memory reference instruction after the second, fetched memory reference instruction if the first tag provided from said tag store means and associated with said first instruction is different than the second tag provided from said tag store means and associated with said second instruction.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-07 | 2000-10-07 | 2001-04-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-07 | 2004-10-07 | 2005-04-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-07 | 2008-10-07 | 2009-04-08 | $7700.00 | Window Closed / Lapsed |