Buck converter with operating mode automatically determined by the load level

Claim 2

A DC-to-DC converter having a power section comprising a switch having a first node and a second node and capable of switching at a frequency established by a timing signal; an output buffer capacitor coupled between said second node and a reference potential; a recirculation diode coupled between said second node and said reference potential; a control and voltage stabilization section coupled between said second node and a control terminal of said switch comprising a first control loop having an error amplifier coupled to said second node and a PWM control comparator coupled to said error amplifier for controlling the duty-cycle of said switch in function of the output voltage, a second control loop having a threshold comparator coupled to said first control loop for controlling the turning-on and turning-off of said switch in function of the output voltage; and means for monitoring the load level of the converter, for disabling said first control loop and enabling said second control loop when the load level of the converter drops below a preset threshold, and for enabling said first control loop and disabling said second control loop when the load level rises above a preset threshold.

Claim 3

The converter of claim 1, wherein said preset thresholds of the level of load are implemented without using sensing resistances of the output current by establishing a reference duty-cycle that is comparable with the current duty-cycle.

Claim 4

The converter of claim 2, wherein said reference duty-cycle has a value comprised between 30% and 80% of a steady state duty-cycle of the converter in a continuous mode of operation under control of said first control loop.

Claim 5

A DC-to-DC static converter comprising a power section having a control node and an output node that includes at least a switch capable of switching at a frequency set by a clock signal, a storing capacitor, a recirculation diode; a control and output voltage stabilization section coupled between said control node and said output node which comprises a first control loop that includes an error amplifier having an input coupled to said output node and a PWM control comparator coupled to said error amplifier and capable of controlling the duty-cycle of said switch in function of the output voltage; a driving circuit of said switch comprising a logic AND gate coupled PWM comparator, receiving through a first input a first logic signal output by said PWM control comparator and having an output connected to a set input of a first latch circuit having a reset terminal to which said clock signal is applied, the output signal of the latch circuit controlling the state of said switch; a first logic circuit capable of generating a second logic signal representative of a reference duty-cycle; a second logic circuit capable of comparing said second logic signal and a first logic signal representative of the current duty-cycle of the converter and generating a third, logic set signal for a second mode latch, the output signal of which enables or disables said error amplifier and said PWM comparator when the current duty-cycle drops below said reference duty-cycle; a hysteresis comparator, coupled to and enabled by said error amplifier and PWM comparator disabling signal, capable of generating a fourth logic signal for turning on and turning off said switch, which is applied to a second input of said AND gate, in function of the dropping of the output voltage of the converter below a first preset minimum reference threshold or of the rising of the output voltage of the converter above a second preset maximum reference threshold; and a third logic circuit capable of determining the duty-cycle of said fourth signal produced by said threshold comparator and generating a fifth logic signal for resetting said second mode latch when the duty-cycle of said fourth logic signal is above a preset threshold thus enabling said error amplifier and said PWM comparator and disabling said comparator.

Claim 6

A DC-to-DC static converter comprising a power section having a control node and an output node that includes at least a switch capable of switching at a frequency set by a clock signal, a storing capacitor, a recirculation diode; a control and output voltage stabilization section coupled between said control node and said output node which comprises a first control loop that includes an error amplifier having an input coupled to said output node and a PWM control comparator coupled to said error amplifier and capable of controlling the duty-cycle of said switch in function of the output voltage; a driving circuit of said switch comprising a logic AND gate coupled PWM comparator, receiving through a first input a first logic signal output by said PWM control comparator and having an output connected to a set input of a first latch circuit having a reset terminal to which said clock signal is applied, the output signal of the latch circuit controlling the state of said switch; a first logic circuit capable of generating a second logic signal representative of a reference duty-cycle; a second logic circuit capable of comparing said second logic signal and a first logic signal representative of the current duty-cycle of the converter and generating a third, logic set signal for a second mode latch, the output signal of which enables or disables said error amplifier and said PWM comparator when the current duty-cycle drops below said reference duty-cycle; a hysteresis comparator, coupled to and enabled by said error amplifier and PWM comparator disabling signal, capable of generating a fourth logic signal for turning on and turning off said switch, which is applied to a second input of said AND gate, in function of the dropping of the output voltage of the converter below a first preset minimum reference threshold or of the rising of the output voltage of the converter above a second preset maximum reference threshold; and a third logic circuit capable of determining the duty-cycle of said fourth signal produced by said threshold comparator and generating a fifth logic signal for resetting said second mode latch when the duty-cycle of said fourth logic signal is above a preset threshold thus enabling said error amplifier and said PWM comparator and disabling said comparator.

Claim 7

The converter of claim 4, wherein said first logic signal generates a signal representative of a reference constant duty-cycle, which varies with the varying of the supply voltage.

Claim 8

The converter of claim 4, wherein said second logic circuit has means for producing a certain hysteresis in the change of state of said third logic signal that sets said second mode latch.

Claim 9

A DC-to-DC converter comprising a power switch capable of intermittently connecting a first terminal of an inductor to a supply node wherein a second terminal of said inductor is connected to a terminal of an output capacitor; a PWM control network connected to control said power switch; a hysteresis control network connected to control said power switch; circuitry connected to monitor the duty cycle of the signal controlling said power switch and to give control of said power switch to said PWM control network when said duty cycle is greater than a preset value and to give control of said power switch to said hysteresis control network when said duty cycle is less than said preset value.

Claim 10

A DC-to-DC converter comprising a power switch capable of intermittently connecting a first terminal of an inductor to a supply node wherein a second terminal of said inductor is connected to a terminal of an output capacitor; a PWM control network connected to control said power switch; a hysteresis control network connected to control said power switch; circuitry connected to monitor the duty cycle of the signal controlling said power switch and to give control of said power switch to said PWM control network when said duty cycle is greater than a preset value and to give control of said power switch to said hysteresis control network when said duty cycle is less than said preset value.

Claim 13

The method of claim 8 wherein the step of controlling said DC-to-DC converter is effected by comparing the duty-cycle of said driving signal of the currently active control loop with a reference value.

Claim 14

The method of claim 8 wherein said preset value has a value comprised between 30% and 80% of a steady state duty-cycle of the converter in a continuous mode of operation under control of said first control loop.