Time skewing arrangement for operating memory in synchronism with a data processor

Claim 2

A data processing system comprising: a plurality of synchronous random access memory devices, each memory device including at least one array of memory cells; a digital processor for producing address signals, data signals, and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices; and a time skewing circuit, interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different ones of the synchronous random access memory devices, for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage devices included within the time skewing circuit, and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices.

Claim 3

A data processing system, in accordance with claim 1, wherein the time skewing circuit is arranged for receiving and storing memory clock delay data and, in response to the memory clock delay data, imparts different delay times into different memory clock signals being applied to different ones of the synchronous random access memory devices; and the time skewing circuit is arranged for receiving and storing read delay data and, in response to the read delay data, imparts different read delay times into different read enable signals being applied to different ones of the data storage devices.

Claim 4

A data processing system, in accordance with claim 2, further comprising: an input peripheral circuit for supplying data to the digital processor; an output peripheral circuit for receiving data from the digital processor; and a clock signal generator for applying a system clock signal to the data processor, to the time skewing circuit, to the input peripheral circuit, and to the output peripheral circuit to operate the data processor, the time skewing circuit, the input peripheral circuit, and the output peripheral circuit in synchronism.

Claim 5

An electrical circuit module comprising: a circuit board; a plurality of synchronous random access memory devices, each memory device including at least one array of memory cells and being fixed to the circuit board; a time skewing circuit, fixed to the circuit board and interconnected with the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different ones of the memory devices, for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage devices included within the time skewing circuit, and for imparting a uniform increment of delay time into write enable signals for loading data into the data storage devices of the time skewing circuit.

Claim 6

An electrical circuit module comprising: a circuit board; a plurality of synchronous random access memory devices, each memory device including at least one array of memory cells and being fixed to the circuit board; a time skewing circuit, fixed to the circuit board and interconnected with the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different ones of the memory devices, for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage devices included within the time skewing circuit, and for imparting a uniform increment of delay time into write enable signals for loading data into the data storage devices of the time skewing circuit.

Claim 7

The circuit module of claim 4 wherein the time skewing circuit includes a plurality of delay paths which are permanently burned-in or fused to provide different desired delays in different paths through the time skewing circuit.

Claim 8

The circuit module of claim 4 wherein the time skewing circuit includes a plurality of delay paths which are alterably programmed to provide different desired delays in different paths through the time skewing circuit.

Claim 9

An electrical circuit module comprising: a circuit board; a plurality of synchronous memory devices fixed to the circuit board; a time skewing circuit fixed to the circuit board; an address bus, fixed to the circuit board and interconnecting the time skewing circuit with the plurality of memory devices; a data bus, fixed to the circuit board and interconnecting the time skewing circuit with the plurality of memory devices; a clock bus, fixed to the circuit board and interconnecting the time skewing circuit with the plurality of memory devices; and a control bus, fixed to the circuit board and interconnecting the time skewing circuit with the plurality of memory devices.

Claim 10

An electrical circuit module comprising: a circuit board; a plurality of synchronous memory devices fixed to the circuit board; a time skewing circuit fixed to the circuit board; an address bus, fixed to the circuit board and interconnecting the time skewing circuit with the plurality of memory devices; a data bus, fixed to the circuit board and interconnecting the time skewing circuit with the plurality of memory devices; a clock bus, fixed to the circuit board and interconnecting the time skewing circuit with the plurality of memory devices; and a control bus, fixed to the circuit board and interconnecting the time skewing circuit with the plurality of memory devices.

Claim 11

A data processing system comprising: a plurality of synchronous memory devices, each memory device including at least one array of memory cells; a digital processor for producing address signals, data signals, and control signals to be transmitted to the plurality of synchronous memory devices and for receiving data signals read from the plurality of synchronous memory devices; and a time skewing circuit, interposed between the digital processor and the plurality of synchronous memory devices for imparting different increments of delay time into memory clock signals transmitted to different ones of the synchronous memory devices, for imparting different increments of delay time into read enable signals, for loading data read from the synchronous memory devices into data storage devices included within the time skewing circuit, and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the synchronous memory devices.

Claim 12

A data processing system comprising: a plurality of synchronous memory devices, each memory device including at least one array of memory cells; a digital processor for producing address signals, data signals, and control signals to be transmitted to the plurality of synchronous memory devices and for receiving data signals read from the plurality of synchronous memory devices; and a time skewing circuit, interposed between the digital processor and the plurality of synchronous memory devices for imparting different increments of delay time into memory clock signals transmitted to different ones of the synchronous memory devices, for imparting different increments of delay time into read enable signals, for loading data read from the synchronous memory devices into data storage devices included within the time skewing circuit, and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the synchronous memory devices.

Claim 13

A data processing system, in accordance with claim 8, wherein the time skewing circuit is arranged for receiving and storing memory clock delay data and, in response to the memory clock delay data, imparts different delay times into different memory clock signals being applied to different ones of the synchronous memory devices; and the time skewing circuit is arranged for receiving and storing read delay data and, in response to the read delay data, imparts different read delay times into different read enable signals being applied to different ones of the data storage devices.

Claim 14

A data processing system, in accordance with claim 9, further comprising: an input peripheral circuit for supplying data to the digital processor; an output peripheral circuit for receiving data from the digital processor; and a clock signal generator for applying a system clock signal to the data processor, to the time skewing circuit, to the input peripheral circuit, and to the output peripheral circuit to operate the data processor, the time skewing circuit, the input peripheral circuit, and the output peripheral circuit in synchronism.

Claim 15

An electrical circuit module comprising: a circuit board; a plurality of synchronous memory devices, each memory device including at least one array of memory cells and being fixed to the circuit board; a time skewing circuit, fixed to the circuit board and interconnected with the plurality of synchronous memory devices for imparting different increments of delay time into memory clock signals transmitted to different ones of the synchronous memory devices, for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage devices included within the time skewing circuit, and for imparting a uniform increment of delay time into write enable signals for loading data into the data storage devices of the time skewing circuit.

Claim 16

An electrical circuit module comprising: a circuit board; a plurality of synchronous memory devices, each memory device including at least one array of memory cells and being fixed to the circuit board; a time skewing circuit, fixed to the circuit board and interconnected with the plurality of synchronous memory devices for imparting different increments of delay time into memory clock signals transmitted to different ones of the synchronous memory devices, for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage devices included within the time skewing circuit, and for imparting a uniform increment of delay time into write enable signals for loading data into the data storage devices of the time skewing circuit.

Claim 17

The circuit module of claim 11 wherein the time skewing circuit includes a plurality of delay paths which are permanently burned-in or fused to provide different desired delays in different paths through the time skewing circuit.

Claim 18

The circuit module of claim 11 wherein the time skewing circuit includes a plurality of delay paths which are alterably programmed to provide different desired delays in different paths through the time skewing circuit.

Claim 19

An electrical circuit module comprising: a circuit board; a plurality of synchronous memory devices fixed to the circuit board; a time skewing circuit fixed to the circuit board; an address bus, fixed to the circuit board and interconnecting the time skewing circuit with the plurality of synchronous memory devices; a data bus, fixed to the circuit board and interconnecting the time skewing circuit with the plurality of synchronous memory devices; a clock bus, fixed to the circuit board and interconnecting the time skewing circuit with the plurality of synchronous memory devices; and a control bus, fixed to the circuit board and interconnecting the time skewing circuit with the plurality of synchronous memory devices.

Claim 20

An electrical circuit module comprising: a circuit board; a plurality of synchronous memory devices fixed to the circuit board; a time skewing circuit fixed to the circuit board; an address bus, fixed to the circuit board and interconnecting the time skewing circuit with the plurality of synchronous memory devices; a data bus, fixed to the circuit board and interconnecting the time skewing circuit with the plurality of synchronous memory devices; a clock bus, fixed to the circuit board and interconnecting the time skewing circuit with the plurality of synchronous memory devices; and a control bus, fixed to the circuit board and interconnecting the time skewing circuit with the plurality of synchronous memory devices.