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US5614838A
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Reduced power apparatus and method for testing high speed components
Assignee: International Business Machines Corp
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Filing: 1995-11-03
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Granted: 1997-03-25
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Expires: 2015-11-03
Abstract
Abstract A system for testing a high speed integrated circuit includes a test device having a test clock with a first maximum frequency for performing level sensitive scan design (LSSD) testing of the integrated circuit device under test, a frequency multiplier circuit for multiplying the test clock signal to a higher second frequency capable of operating the device under test, and a finite state machine for generating a first internal clock for testing the device under test. In a practical embodiment, the internal clock speed may be running at a frequency many multiples of the test clock. Alternatively, a method of testing a device under test (DUT) at design speed includes running a predetermined group of tests with a test device operating at a lower speed than the design speed; incorporating LSSD or boundary scan test techniques in the device under test, together with a frequency multiplying device; generating a global clock for the device under test from the frequency multiplying circuit and using a finite state machine as a synchronizer and pulse generator to control a capture clock with respect to the global clock.
Inventors
- 👤 Talal K. Jaber
- 👤 Steven A. Schmidt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 13:56
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318577; G01R31/2801; G01R31/281; G01R31/2815; G01R31/31721; G01R31/318552
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
102 words
Apparatus for reduced power dissipation testing a high speed electronic component, comprising: a test device, for generating a test clock signal having a first frequency, said test device performing a multiphase test of said high speed electronic component; means for generating a second frequency clock signal capable of operating said electronic component at a predetermined high speed rate; and test control logic for controlling application of said second frequency test clock signal to circuits on said high speed electronic component to stop said second frequency clock signal during one phase of said multiphase test to reduce power dissipation in said electronic component.
Claim 2
Dependent Claim
102 words
Apparatus for reduced power dissipation testing a high speed electronic component, comprising: a test device, for generating a test clock signal having a first frequency, said test device performing a multiphase test of said high speed electronic component; means for generating a second frequency clock signal capable of operating said electronic component at a predetermined high speed rate; and test control logic for controlling application of said second frequency test clock signal to circuits on said high speed electronic component to stop said second frequency clock signal during one phase of said multiphase test to reduce power dissipation in said electronic component.
Claim 3
Dependent Claim
26 words
Apparatus for testing a high speed electronic component, according to claim 1, wherein said multiphase test comprises a scan test phase and a system test phase.
Claim 4
Dependent Claim
41 words
Apparatus for testing a high speed electronic component, according to claim 1, wherein said test control logic further comprises: means responsive to a test phase signal for stopping a system clock signal from being applied to said high speed electronic component.
Claim 5
Dependent Claim
32 words
Apparatus for testing a high speed electronic component, according to claim 2, wherein said test control logic further comprises: means for reducing the frequency of a scan clock during said scan phase.
Claim 6
Dependent Claim
39 words
Apparatus for testing a high speed electronic component, according to claim 2, wherein said test control logic further comprises: means for inserting a dead clock interval between pulses of a first scan clock signal and a second clock signal.
Claim 7
Independent Claim
90 words
A method for reducing power dissipation in a high speed electronic component during a test of said high speed electronic component, comprising the steps of: generating a test phase signal indicating which phase of a multiphase test is to be performed on said high speed electronic component; stopping application of a first clock signal to said high speed electronic component during a first phase of said multiphase test; and allowing application of a first clock signal to said high speed electronic component during a second phase of said multiphase test.
Claim 8
Independent Claim
90 words
A method for reducing power dissipation in a high speed electronic component during a test of said high speed electronic component, comprising the steps of: generating a test phase signal indicating which phase of a multiphase test is to be performed on said high speed electronic component; stopping application of a first clock signal to said high speed electronic component during a first phase of said multiphase test; and allowing application of a first clock signal to said high speed electronic component during a second phase of said multiphase test.
Claim 9
Dependent Claim
45 words
A method, according to claim 6, wherein said stopping step further comprises the steps of: generating a stop clock signal in response to said test phase signal; and receiving an acknowledgement signal indicating that said stop clock signal was received by a clock generation circuit.
Claim 10
Dependent Claim
24 words
A method, according to claim 6, further comprising the step of: reducing a frequency of a scan clock signal during a first test phase.
Claim 11
Dependent Claim
39 words
A method, according to claim 6, further comprising the step of: inserting a dead clock interval between pulses of a first scan clock signal and a second clock signal to reduce power dissipation in said high speed electronic component.
References Cited (Backward Citations)
US5517109A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-24 | 2000-09-23 | 2001-03-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-24 | 2004-09-23 | 2005-03-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-24 | 2008-09-23 | 2009-03-25 | $7700.00 | Window Closed / Lapsed |