US5614740A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High-speed peristaltic CCD imager with GaAs fet output
Assignee: Q Dot Inc
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Filing: 1994-11-30
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Granted: 1997-03-25
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Expires: 2014-11-30
Abstract
Abstract An improved CCD imaging array is disclosed which is capable of operating at 10,000 frames-per-second. The imager consists of an array of 512×512 pixels having 16 serial output channels which provides a composite output data rate up to 250 Megasamples/second. The serial output registers are constructed from peristaltic CCDs, each having a GaAs FET output circuit bump-mounted to the silicon substrate. A four-layer pinned photodiode is utilized as the photodetector, and each photodiode has its own antiblooming drain. The antiblooming gates double as an optical shuttering device. Sample-and-hold output circuitry is also provided.
Inventors
- 👤 David W. Gardner
- 👤 Thomas E. Linnenbrink
- 👤 Stephen D. Gaalema
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 16:03
CPC Classifications
H; H10; H10D; H10D44/00; H10D44/40; H10D44/45; H10D44/454; H10F; H10F39/00; H10F39/10; H10F39/12; H10F39/15; H10F39/153
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
127 words
A CCD imaging array of the interline transfer type comprising: a silicon semiconductor substrate; an array of photodiodes disposed on said substrate which produce charge packets when exposed to light; a plurality of buried channel CCD interline transfer registers disposed on said substrate; means for supplying a two-phase clock to the plurality of buried channel CCD interline transfer registers for transferring said charge packets from said photodetectors; a plurality of profiled peristaltic CCD serial output registers disposed on said substrate; means for supplying a four-phase clock to the plurality of profiled CCD output registers for transferring said charge packets from said interline transfer registers; and a plurality of output circuits for transferring said charge packets from said serial output registers to provide a plurality of output signals.
Claim 2
Dependent Claim
127 words
A CCD imaging array of the interline transfer type comprising: a silicon semiconductor substrate; an array of photodiodes disposed on said substrate which produce charge packets when exposed to light; a plurality of buried channel CCD interline transfer registers disposed on said substrate; means for supplying a two-phase clock to the plurality of buried channel CCD interline transfer registers for transferring said charge packets from said photodetectors; a plurality of profiled peristaltic CCD serial output registers disposed on said substrate; means for supplying a four-phase clock to the plurality of profiled CCD output registers for transferring said charge packets from said interline transfer registers; and a plurality of output circuits for transferring said charge packets from said serial output registers to provide a plurality of output signals.
Claim 3
Dependent Claim
33 words
The CCD imaging array according to claim 1, wherein each of said photodiodes of the array of photodiodes is a four-layer pinned photodiode having conductivity types and concentrations arranged as: P+/N-/N--/P or N+/P-/P--/N.
Claim 4
Dependent Claim
64 words
The CCD imaging array according to claim 1, wherein each of said photodiodes includes an antiblooming drain, and antiblooming gate operatively coupling said charge packets to said antiblooming drain, and a variable pulse width gate signal operatively coupled to said antiblooming gate, wherein said antiblooming gate selectively discharges said charge packets via said antiblooming drain when said gate signal is in an active state.
Claim 5
Dependent Claim
21 words
The apparatus as in claim 1 further comprising an antiblooming drain associated with each photodiode of the array of pinned photodiodes.
Claim 6
Dependent Claim
24 words
The apparatus as in claim 4 further comprising a shutter control for activating the antiblooming drain during a variable portion of each frame period.
Claim 7
Dependent Claim
136 words
A CCD imaging array of the interline transfer type comprising: a silicon semiconductor substrate; an array of photodiodes disposed on said substrate which produce charge packets when exposed to light; a plurality of buried channel CCD interline transfer registers disposed on said substrate; means for supplying a two-phase clock to the plurality of buried channel CCD interline transfer registers for transferring said charge packets from said photodiode; a plurality of profiled peristaltic CCD serial output registers disposed on said substrate; means for supplying a four-phase clock to the plurality of profiled peristaltic CCD serial output registers for transferring said charge packets from said interline transfer registers; an antiblooming structure associated with each photodiode; and a plurality of output circuits for transferring said charge packets from said serial output registers to provide a plurality of output signals.
Claim 8
Dependent Claim
136 words
A CCD imaging array of the interline transfer type comprising: a silicon semiconductor substrate; an array of photodiodes disposed on said substrate which produce charge packets when exposed to light; a plurality of buried channel CCD interline transfer registers disposed on said substrate; means for supplying a two-phase clock to the plurality of buried channel CCD interline transfer registers for transferring said charge packets from said photodiode; a plurality of profiled peristaltic CCD serial output registers disposed on said substrate; means for supplying a four-phase clock to the plurality of profiled peristaltic CCD serial output registers for transferring said charge packets from said interline transfer registers; an antiblooming structure associated with each photodiode; and a plurality of output circuits for transferring said charge packets from said serial output registers to provide a plurality of output signals.
Claim 9
Dependent Claim
33 words
The CCD imaging array according to claim 6, wherein each of said photodiodes of the array of photodiodes is a four-layer pinned photodiode having conductivity types and concentrations arranged as: P+/N-/N--/P or N+/P-/P--/N.
Claim 10
Dependent Claim
64 words
The CCD imaging array according to claim 6, wherein each antiblooming structure further comprises an antiblooming drain, and antiblooming gate operatively coupling said charge packets to said antiblooming drain, and a variable pulse width gate signal operatively coupled to said antiblooming gate, wherein said antiblooming gate selectively discharges said charge packets via said antiblooming drain when said gate signal is in an active state.
Claim 11
Dependent Claim
111 words
The CCD imaging structure according to claim 6 wherein the antiblooming structure further comprises: an antiblooming drain disposed substantially adjacent each photodetector; a source of constant DC potential connected to each antiblooming drain, said source being of the type which will remove any charge disposed within said drains; a gate disposed between each photodetector and its corresponding antiblooming drain, each gate constructed and arranged to control the charge transfer from each photodetector to each drain in response to a gating signal; and means for providing said gating signal to said gates, said gating signal having a predefined period substantially the same as said frame rate, and having a variable duty cycle.
Claim 12
Dependent Claim
113 words
A solid state imaging array comprising: an array of photodetectors which produce charge packets when exposed to light; a plurality of CCD shift registers for transferring said charge packets from said photodetectors to an imaging array output; means for supplying a two-phase clock to at least some of the plurality of CCD shift registers for urging said charge packets towards the imaging array output; means for supplying a four-phase clock to at least some other of the CCD shift registers for urging said charge packets towards the imaging array output; and means for outputting at the imaging array output a voltage signal from said imaging array in response to said transferred charge packets.
Claim 13
Dependent Claim
113 words
A solid state imaging array comprising: an array of photodetectors which produce charge packets when exposed to light; a plurality of CCD shift registers for transferring said charge packets from said photodetectors to an imaging array output; means for supplying a two-phase clock to at least some of the plurality of CCD shift registers for urging said charge packets towards the imaging array output; means for supplying a four-phase clock to at least some other of the CCD shift registers for urging said charge packets towards the imaging array output; and means for outputting at the imaging array output a voltage signal from said imaging array in response to said transferred charge packets.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-24 | 2000-09-23 | 2001-03-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-24 | 2004-09-23 | 2005-03-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-24 | 2008-09-23 | 2009-03-25 | $7700.00 | Window Closed / Lapsed |