US5613102A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of compressing data for use in performing VLSI mask layout verification
Assignee: Cadence Design Systems Inc
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Filing: 1995-10-19
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Granted: 1997-03-18
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Expires: 2015-10-19
Abstract
Abstract A method of compressing data used in integrated circuit (IC) layout verifications includes the steps of identifying each circuit component from each layer of the IC chip; sorting each circuit component in an established order; identifying predetermined parameters for each component; determining the difference in value of the parameters for each pair of components in successive order; and storing the difference values for each pair of components.
Inventors
- 👤 Kuang-Wei Chiang
- 👤 Chi-Yuan Lo
- 👤 Doowan Paik
- 👤 Shun-Lin Su
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 14:29
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/398
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
263 words
A method of compressing data used in IC layout verifications of an IC chip comprising: a) identifying each circuit component from each layer of the IC chip; b) applying a range compression transformation to uncompressed data which reduces the value of the data by a predetermined order of magnitude; c) arranging each circuit component in an established order based on the physical location of the circuit component within the IC chip; d) identifying predetermined parameters for each component; e) performing a differential measurement to determine the difference in value of the parameters for a pair of components in successive order, said differential measurement resulting in a compressed data representation of the parameter values for a second component relative to a first component, said first and second components comprising the pair of components, said second component being a component for which the compressed data representation is currently being recorded and the first component being a component for which a compressed data representation has previously been recorded, said compressed data representation representing the minimal amount of information required to retrieve the parameter values for the second component, said data representation containing relational information for the pair of components, said differential measurement acting as a mechanism for compressing the data representing the circuit components; f) identifying rectangles contained within a given layer of the chip which are substantially identical; g) encoding common data attributes in a compact form; h) storing the compressed data representation for the second component; and i) repeating steps e) and h) for each successive pair of components contained in the IC chip.
Claim 2
Independent Claim
263 words
A method of compressing data used in IC layout verifications of an IC chip comprising: a) identifying each circuit component from each layer of the IC chip; b) applying a range compression transformation to uncompressed data which reduces the value of the data by a predetermined order of magnitude; c) arranging each circuit component in an established order based on the physical location of the circuit component within the IC chip; d) identifying predetermined parameters for each component; e) performing a differential measurement to determine the difference in value of the parameters for a pair of components in successive order, said differential measurement resulting in a compressed data representation of the parameter values for a second component relative to a first component, said first and second components comprising the pair of components, said second component being a component for which the compressed data representation is currently being recorded and the first component being a component for which a compressed data representation has previously been recorded, said compressed data representation representing the minimal amount of information required to retrieve the parameter values for the second component, said data representation containing relational information for the pair of components, said differential measurement acting as a mechanism for compressing the data representing the circuit components; f) identifying rectangles contained within a given layer of the chip which are substantially identical; g) encoding common data attributes in a compact form; h) storing the compressed data representation for the second component; and i) repeating steps e) and h) for each successive pair of components contained in the IC chip.
Claim 3
Dependent Claim
19 words
The method according to claim 1 wherein said predetermined parameters represent geometric data describing each component in the chip.
Claim 4
Dependent Claim
34 words
The method according to claim 2 wherein each component is represented by at least one rectangle and said identifying step further comprises: identifying coordinate data for each component within the chip representing each rectangle.
Claim 5
Dependent Claim
19 words
The method according to claim 3 wherein said coordinate data for a given rectangle comprises diagonally opposite coordinate pairs.
Claim 6
Dependent Claim
13 words
The method according to claim 1 wherein said predetermined parameters represent parasitic data.
Claim 7
Dependent Claim
13 words
The method according to claim 1 wherein said predetermined parameters represent transistor data.
Claim 8
Dependent Claim
22 words
The method according to claim 1 further comprising the step of scaling down each parameter value by a predetermined order of magnitude.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-17 | 2000-09-16 | 2001-03-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-17 | 2004-09-16 | 2005-03-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-17 | 2008-09-16 | 2009-03-18 | $7700.00 | Window Closed / Lapsed |