Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
112 words
A method of vector quantizing a video frame using a vector quantization codebook, wherein the video frame is segmented into a plurality of coding blocks, the method comprising the steps of: transferring a predetermined portion of the vector quantization codebook into a first section of a first cache memory; performing a vector quantization process for a predetermined number of the plurality of coding blocks with respect to the portion of the vector quantization codebook transferred to the first section of the first cache memory; and transferring a next predetermined portion of the codebook into a second section of the first cache memory after initiating the step of performing a vector quantization process.
Claim 2
Independent Claim
112 words
A method of vector quantizing a video frame using a vector quantization codebook, wherein the video frame is segmented into a plurality of coding blocks, the method comprising the steps of: transferring a predetermined portion of the vector quantization codebook into a first section of a first cache memory; performing a vector quantization process for a predetermined number of the plurality of coding blocks with respect to the portion of the vector quantization codebook transferred to the first section of the first cache memory; and transferring a next predetermined portion of the codebook into a second section of the first cache memory after initiating the step of performing a vector quantization process.
Claim 3
Dependent Claim
53 words
The method of claim 1 wherein the step of transferring a next predetermined portion of the vector quantization codebook comprises the step of completing transfer of the next predetermined portion of the vector quantization codebook at the same time as or prior to completion of the step of performing a vector quantization process.
Claim 4
Dependent Claim
55 words
The method of claim 1 further comprising the step of selecting the predetermined number of the plurality of coding blocks such that the step of transferring a next predetermined portion of the vector quantization codebook is completed at the same time as or prior to completion of the step of performing a vector quantization process.
Claim 5
Dependent Claim
56 words
The method of claim 1 further comprising the step of selecting the predetermined number of the plurality of coding blocks such that the time required to perform the step of performing a vector quantization process is equal to the time required to perform the step of transferring a next predetermined portion of the vector quantization codebook.
Claim 6
Dependent Claim
40 words
The method of claim 1 further comprising the step of performing at least the steps of performing a vector quantization process and transferring a next predetermined portion of the vector quantization codebook using an Integrated Information Technology, Inc., VCP chip.
Claim 7
Dependent Claim
53 words
The method of claim 5 wherein the step of transferring a predetermined portion of the vector quantization codebook into a first section of a first cache memory comprises the step of transferring the predetermined portion of the vector quantization codebook into the DM memory unit of the Integrated Information Technology, Inc., VCP chip.
Claim 8
Dependent Claim
28 words
The method of claim 1 wherein the step of performing a vector quantization process comprises the step of performing a vector quantization process using a predictable search algorithm.
Claim 9
Dependent Claim
36 words
The method of claim 1 further including the step of transferring the predetermined number of the plurality of coding blocks into a second cache memory prior to performing the step of performing a vector quantization process.
Claim 10
Dependent Claim
46 words
The method of claim 1 further comprising the step of repeating the steps of performing a vector quantization process and transferring a next predetermined portion of the vector quantization codebook until the vector quantization process has been performed with respect to the entire vector quantization codebook.
Claim 11
Dependent Claim
47 words
The method of claim 1 wherein the step of transferring a predetermined portion of the vector quantization codebook into a first section of a first cache memory includes the step of transferring a portion of the codebook sufficient to fill one half of the first cache memory.
Claim 12
Dependent Claim
49 words
The method of claim 10 wherein the step of transferring a next predetermined portion of the vector quantization codebook into a second section of the first cache memory includes the step of transferring a portion of the codebook sufficient to fill the remaining half of the first cache memory.
Claim 13
Dependent Claim
47 words
The method of claim 7 wherein the step of performing a vector quantization process comprises the steps of: calculating quantization errors; selecting a codebook entry corresponding to a lowest calculated quantization error; and storing an address associated with the codebook entry corresponding to the lowest quantization error.
Claim 14
Dependent Claim
40 words
The method of claim 1 further including the step of rotating the first cache memory such that addresses previously associated with the second section of the first cache memory are associated with the first section of the first cache memory.
Claim 15
Dependent Claim
45 words
The method of claim 13 further comprising the step of performing at least the steps of performing a vector quantization process, transferring a next predetermined portion of the vector quantization codebook and rotating the first cache memory, using an Integrated Information Technology, Inc., VCP chip.
Claim 16
Dependent Claim
48 words
The method of claim 1 wherein the step of transferring a next predetermined portion of the codebook comprises the step of transferring the next predetermined portion of the codebook into the second section of the first cache memory concurrently with the step of performing the vector quantization process.
Claim 17
Independent Claim
262 words
An apparatus for encoding a video frame comprising: a reference memory storing a plurality of coding blocks corresponding to a video frame in a sequence of video frames and storing a vector quantization codebook; and a video compression processor comprising: (a) a first cache memory; (b) a second cache memory; (c) a sequencer for executing a vector quantization routine; (d) means for transferring specified ones of the plurality of coding blocks from the reference memory to the first cache memory; (e) means for transferring portions of the vector quantization codebook from the reference memory to the second cache memory; (f) means for instructing a predetermined number of the plurality of coding blocks to be transferred from the reference memory to the first cache memory; (g) means for instructing a portion of the vector quantization codebook to be transferred from the reference memory to a first section of the first cache memory; (h) means for instructing the sequencer to perform the vector quantization routine for the predetermined number of the plurality of coding blocks with respect to the portion of the vector quantization codebook currently in the first section of the vector quantization codebook; (i) means for instructing a next portion of the vector quantization codebook to be transferred to a second section of the second cache memory while the vector quantization routine is being performed; and (j) means for instructing the second cache memory to be rotated such that addresses previously associated with the second section of the second cache memory are associated with the first section of the second cache memory.
Claim 18
Independent Claim
262 words
An apparatus for encoding a video frame comprising: a reference memory storing a plurality of coding blocks corresponding to a video frame in a sequence of video frames and storing a vector quantization codebook; and a video compression processor comprising: (a) a first cache memory; (b) a second cache memory; (c) a sequencer for executing a vector quantization routine; (d) means for transferring specified ones of the plurality of coding blocks from the reference memory to the first cache memory; (e) means for transferring portions of the vector quantization codebook from the reference memory to the second cache memory; (f) means for instructing a predetermined number of the plurality of coding blocks to be transferred from the reference memory to the first cache memory; (g) means for instructing a portion of the vector quantization codebook to be transferred from the reference memory to a first section of the first cache memory; (h) means for instructing the sequencer to perform the vector quantization routine for the predetermined number of the plurality of coding blocks with respect to the portion of the vector quantization codebook currently in the first section of the vector quantization codebook; (i) means for instructing a next portion of the vector quantization codebook to be transferred to a second section of the second cache memory while the vector quantization routine is being performed; and (j) means for instructing the second cache memory to be rotated such that addresses previously associated with the second section of the second cache memory are associated with the first section of the second cache memory.
Claim 19
Dependent Claim
55 words
The apparatus of claim 16 wherein the means for instructing a next portion of the vector quantization codebook to be transferred comprises a controller programmed to direct complete transfer of the next portion of the vector quantization codebook to the second section of the second cache memory prior to completion of the vector quantization routine.
Claim 20
Dependent Claim
38 words
The apparatus of claim 17 wherein the video compression processor further comprises an offset register connected between the sequencer and the second cache memory for rotating the second cache memory according to information stored in the offset register.
Claim 21
Dependent Claim
18 words
The apparatus of claim 17 wherein the video compression processor comprises an Integrated Information Technology, Inc., VCP chip.
Claim 22
Dependent Claim
37 words
The apparatus of claim 17 wherein the video compression processor further comprises an arithmetic logic unit for calculating quantization errors and selecting a codebook entry with a lowest quantization error as part of the vector quantization routine.
Claim 23
Dependent Claim
30 words
The apparatus of claim 20 wherein the video compression processor further comprises a register file for storing an address associated with the codebook entry resulting in the lowest quantization error.
Claim 24
Dependent Claim
45 words
The apparatus of claim 17 wherein the video compression processor further comprises means for calculating quantization errors, means for selecting a codebook entry with a lowest quantization error, and means for storing an address associated with the codebook entry resulting in the lowest quantization error.
Claim 25
Dependent Claim
29 words
The apparatus of claim 17 wherein the second cache memory comprises at least two ports to permit simultaneous reading and writing to and from the second cache memory, respectively.
Claim 26
Dependent Claim
38 words
The apparatus of claim 17 wherein the first cache memory and the second cache memory each consist of a number of memory bytes several orders of magnitude smaller than the number of memory bytes in the reference memory.
Claim 27
Dependent Claim
27 words
The apparatus of claim 17 wherein the second cache memory consists of 1440 bytes of memory and wherein the first cache memory consists of 1024 memory bytes.
Claim 28
Dependent Claim
52 words
The apparatus of claim 16 wherein the means for instructing a predetermined number of the plurality of coding blocks to be transferred memory is programmed to select the predetermined number such that transfer of the next portion of the vector quantization codebook is completed prior to completion of the vector quantization routine.
Claim 29
Dependent Claim
25 words
The apparatus of claim 18 wherein the means for instructing the second cache memory to be rotated controls the information stored in the offset register.
Claim 30
Dependent Claim
14 words
The apparatus of claim 17 wherein the controller is a reduced instruction set microprocessor.
Claim 31
Independent Claim
112 words
A method of vector quantizing a video frame comprising the steps of: segmenting the video frame into a plurality of coding blocks; storing a vector quantization codebook in a reference memory; transferring a predetermined portion of the vector quantization codebook into a first section of a first cache memory; performing a vector quantization process for a predetermined number of the plurality of coding blocks with respect to the portion of the vector quantization codebook transferred to the first section of the first cache memory; and transferring a next predetermined portion of the codebook into a second section of the first cache memory after initiating the step of performing a vector quantization process.
Claim 32
Independent Claim
112 words
A method of vector quantizing a video frame comprising the steps of: segmenting the video frame into a plurality of coding blocks; storing a vector quantization codebook in a reference memory; transferring a predetermined portion of the vector quantization codebook into a first section of a first cache memory; performing a vector quantization process for a predetermined number of the plurality of coding blocks with respect to the portion of the vector quantization codebook transferred to the first section of the first cache memory; and transferring a next predetermined portion of the codebook into a second section of the first cache memory after initiating the step of performing a vector quantization process.