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US5612713A
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Digital micro-mirror device with block data loading
Assignee: Texas Instruments Inc
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Filing: 1995-01-06
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Granted: 1997-03-18
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Expires: 2015-01-06
Abstract
Abstract A digital micro-mirror device (20) for imaging applications, having an array (21) of mirror elements for forming the image and data loading circuitry (22, 23, 24) for loading data for addressing the mirror elements. The data loading circuitry (22, 23, 24) has a row of shift registers (24), which receive one row of data at a time, which they deliver to latches (23). The latches (23) hold the data on bit-lines, which run down columns of the array (21). The row to be loaded is selected with a row decoder (25). A block load circuit (22), comprised of a shift register (35) and logic gates (33) divides each row of memory cells into blocks (31) and ensures that each block of a row of memory cells is sequentially loaded.
Inventors
- 👤 Rohit L. Bhuva
- 👤 James L. Conner
- 👤 Michael J. Overlauer
- 👤 William R. Townson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 22:26
CPC Classifications
G; G09; G09G; G09G3/00; G09G3/20; G09G3/2085; G09G3/34; G09G2300/00; G09G2300/08; G09G2300/0809; G09G2300/0814; G09G2300/0842; G09G2310/00; G09G2310/02; G09G2310/0264; G09G2310/027; G09G3/2007; G09G3/2018; G09G3/2022; G09G3/3433; G09G3/346
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
186 words
A spatial light modulator (SLM), comprising: an array of pixel-generating elements, each pixel-generating element being individually addressable with data, said array of pixel-generating elements having an associated array of memory cells for storing said data; at least one bit-line associated with each column of memory cells for delivering data to said column of memory cells; a row of shift registers for receiving row data for one row of said array from an external source for delivery to said memory cells; a row of latches for receiving said row data from said shift registers, and for holding said row data on said bit-lines; a block load circuit, interposed between said latches and said memory cells, for sequencing the delivery of said row data to a selected row of said memory cells by delivering a write signal to different blocks of said selected row of memory cells, with each block receiving said write signal at a different time; and a row decoder for delivering a row select signal to said block load circuit for determining which row of said memory cells is said selected row of memory cells.
Claim 2
Dependent Claim
186 words
A spatial light modulator (SLM), comprising: an array of pixel-generating elements, each pixel-generating element being individually addressable with data, said array of pixel-generating elements having an associated array of memory cells for storing said data; at least one bit-line associated with each column of memory cells for delivering data to said column of memory cells; a row of shift registers for receiving row data for one row of said array from an external source for delivery to said memory cells; a row of latches for receiving said row data from said shift registers, and for holding said row data on said bit-lines; a block load circuit, interposed between said latches and said memory cells, for sequencing the delivery of said row data to a selected row of said memory cells by delivering a write signal to different blocks of said selected row of memory cells, with each block receiving said write signal at a different time; and a row decoder for delivering a row select signal to said block load circuit for determining which row of said memory cells is said selected row of memory cells.
Claim 3
Dependent Claim
23 words
The SLM of claim 1, wherein said spatial light modulator is a digital micro-mirror device, and wherein said pixel-generating elements are mirror elements.
Claim 4
Dependent Claim
17 words
The SLM of claim 1, wherein said pixel-generating elements have a one-to-one relationship with said memory cells.
Claim 5
Dependent Claim
25 words
The SLM of claim 1, wherein said pixel-generating elements are in groups, with each group in data communication with only one of said memory cells.
Claim 6
Dependent Claim
31 words
The SLM of claim 1, wherein said block load circuit has a shift register that sequentially delivers a block load signal to a logic gate at the input of each block.
Claim 7
Dependent Claim
31 words
The SLM of claim 1, wherein said block load circuit has a logic gate at the input of each block for receiving said row select signal and said block load signal.
Claim 8
Dependent Claim
53 words
The SLM of claim 1, wherein said block load circuit has a shift register that sequentially delivers a block load signal to a logic gate at the input of each block, said logic gate for outputting said write signal based on the states of said row select signal and said block load signal.
Claim 9
Dependent Claim
20 words
The SLM of claim 1, wherein said bit-lines comprise a bit-line and a complement bit-line to each said memory cell.
Claim 10
Dependent Claim
17 words
The SLM of claim 1, wherein said bit-lines comprise a single bit-line to each said memory cell.
Claim 11
Independent Claim
110 words
A method of loading data to a spatial light modulator having individually addressable pixel-generating elements, comprising the steps of: receiving a row of data into a row of shift registers; delivering said row of data to a row of latches; holding said row of data on bit-lines that run down columns of said pixel-generating elements; selecting a row of pixel-generating elements to be addressed with said row of data by means of a row select signal; sequentially loading memory cells of said row of pixel-generating elements in blocks of said memory cells; and repeating the above steps for different rows of data to be loaded to said spatial light modulator.
Claim 12
Independent Claim
110 words
A method of loading data to a spatial light modulator having individually addressable pixel-generating elements, comprising the steps of: receiving a row of data into a row of shift registers; delivering said row of data to a row of latches; holding said row of data on bit-lines that run down columns of said pixel-generating elements; selecting a row of pixel-generating elements to be addressed with said row of data by means of a row select signal; sequentially loading memory cells of said row of pixel-generating elements in blocks of said memory cells; and repeating the above steps for different rows of data to be loaded to said spatial light modulator.
Claim 13
Dependent Claim
15 words
The method of claim 10, wherein said selecting step is performed with a row decoder.
Claim 14
Dependent Claim
28 words
The method of claim 10, wherein said loading step is performed with a logic gate at the input of each said block that receives said row select signal.
Claim 15
Dependent Claim
45 words
The method of claim 10, wherein said loading step is performed with a logic gate at the input of each said block that receives said row select signal and a load signal that shifts from block to block of the selected row of pixel-generating elements.
Claim 16
Dependent Claim
15 words
The method of claim 13, wherein said load signal is generated with a shift register.
Claim 17
Dependent Claim
17 words
The method of claim 13, wherein said load signal is generated with a D flip-flop shift register.
Claim 18
Dependent Claim
186 words
A digital micro-mirror device (DMD), comprising: an array of mirror elements, each mirror element being individually addressable with data, said array of mirror elements having an associated array of memory cells for storing said data; at least one bit-line associated with each column of memory cells for delivering data to said column of memory cells; a row of shift registers for receiving row data for one row of said array from an external source for delivery to said memory cells; a row of latches for receiving said row data from said shift registers, and for holding said row data on said bit-lines; a block load circuit, interposed between said latches and said memory cells, for sequencing the delivery of said row data to a selected row of said memory cells by delivering a write signal to different blocks of said selected row of memory cells, with each block receiving said write signal at a different time; and a row decoder for delivering a row select signal to said block load circuit for determining which row of said memory cells is said selected row of memory cells.
Claim 19
Dependent Claim
186 words
A digital micro-mirror device (DMD), comprising: an array of mirror elements, each mirror element being individually addressable with data, said array of mirror elements having an associated array of memory cells for storing said data; at least one bit-line associated with each column of memory cells for delivering data to said column of memory cells; a row of shift registers for receiving row data for one row of said array from an external source for delivery to said memory cells; a row of latches for receiving said row data from said shift registers, and for holding said row data on said bit-lines; a block load circuit, interposed between said latches and said memory cells, for sequencing the delivery of said row data to a selected row of said memory cells by delivering a write signal to different blocks of said selected row of memory cells, with each block receiving said write signal at a different time; and a row decoder for delivering a row select signal to said block load circuit for determining which row of said memory cells is said selected row of memory cells.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-17 | 2000-09-16 | 2001-03-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-17 | 2004-09-16 | 2005-03-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-17 | 2008-09-16 | 2009-03-18 | $7700.00 | Window Closed / Lapsed |