Abstract A structure and fabrication method for a thin film transistor suitable for a SRAM memory cell. The thin film transistor structure includes a gate electrode formed to have a groove, a gate insulation film formed on the gate electrode, a semiconductor layer formed in the groove of the gate electrode, and impurity regions formed on opposite sides of the semiconductor layer. The method for fabricating the thin film transistor includes forming a gate electrode and a gate insulation film successively on an insulating substrate so as to have a groove, forming a semiconductor layer on the gate insulation film at a part of the groove, and forming source/drain impurity regions by selective injection of impurity ions into opposite sides of the semiconductor layer.
A thin film transistor structure comprising: an insulating substrate including a trench with a fixed width formed generally parallel to a first axis; a gate electrode formed to have a groove above the trench and to at least the level of the substrate along the first axis on the insulating substrate, wherein the gate electrode is formed on the insulating substrate and in the trench, and is divided in two parts separated in a direction transverse to the first axis by a fixed width; a gate insulation film formed on the gate electrode; a semiconductor layer formed in the groove of the gate electrode, wherein a central portion of the semiconductor layer functions as a channel region; and source and drain impurity regions formed at both longitudinally spaced sides of the semiconductor layer and separated by the channel region.
Claim 2
Dependent Claim
139 words
A thin film transistor structure comprising: an insulating substrate including a trench with a fixed width formed generally parallel to a first axis; a gate electrode formed to have a groove above the trench and to at least the level of the substrate along the first axis on the insulating substrate, wherein the gate electrode is formed on the insulating substrate and in the trench, and is divided in two parts separated in a direction transverse to the first axis by a fixed width; a gate insulation film formed on the gate electrode; a semiconductor layer formed in the groove of the gate electrode, wherein a central portion of the semiconductor layer functions as a channel region; and source and drain impurity regions formed at both longitudinally spaced sides of the semiconductor layer and separated by the channel region.