US5612249A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Post-gate LOCOS
Assignee: Advanced Micro Devices Inc
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Filing: 1996-05-14
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Granted: 1997-03-18
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Expires: 2016-05-14
Abstract
Abstract A method of defining a local oxidation of silicon (LOCOS) field isolation process after a poly gate is deposited. A gate oxide is grown on a silicon substrate, and then poly or amorphous silicon is deposited. A thin layer of PECVD or LPCVD oxide is deposited on the poly, and LPCVD nitride is then deposited as a hard mask. A device active area is defined by photoresist mask and plasma etch. The layers may either be etched down to the silicon surface, or the silicon surface may be further etched to create a recessed silicon region. An oxide layer is grown on the exposed sidewalls of the poly, and another layer of nitride is deposited. The nitride is etched to form a nitride spacer, and a field oxide is grown. A field isolation implant is formed, followed by stripping the nitride space. The oxide layer is removed, reexposing the poly. Another layer of poly and WSi film is deposited, and gate and interconnects are defined by applying a gate mask and etch. An alternate approach of self-aligned silicide gate, junction and interconnect can be formed without using WSi by depositing Ti after the gate is defined. N-LDD and P-LDD implants are performed by masks, followed by an oxide spacer being formed. N+ and p+ junctions are then formed by separate masks and implants.
Inventors
- 👤 Yu Sun
- 👤 Yowjuang W. Liu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 06:54
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; H10D64/021; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/10; H10W10/13
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
109 words
A method of fabricating an integrated circuit semiconductor device having a plurality of field effect transistors (FETs) in and on a silicon substrate with local oxidation of silicon (LOCOS) as field oxide isolating regions between the FETs, the method comprising the steps of: a) forming a gate oxide layer on a top surface of the substrate; b) forming a polysilicon layer on said gate oxide layer; c) etching said gate oxide layer and said polysilicon layer to form gate structures for said FETs; d) surrounding said gate structures with an oxidation mask; and e) forming the LOCOS field oxide isolation regions by growing an oxide layer between the FETs.
Claim 2
Independent Claim
109 words
A method of fabricating an integrated circuit semiconductor device having a plurality of field effect transistors (FETs) in and on a silicon substrate with local oxidation of silicon (LOCOS) as field oxide isolating regions between the FETs, the method comprising the steps of: a) forming a gate oxide layer on a top surface of the substrate; b) forming a polysilicon layer on said gate oxide layer; c) etching said gate oxide layer and said polysilicon layer to form gate structures for said FETs; d) surrounding said gate structures with an oxidation mask; and e) forming the LOCOS field oxide isolation regions by growing an oxide layer between the FETs.
Claim 3
Dependent Claim
20 words
The method according to claim 1, further comprising the step of: f) forming source and drain regions for the FETs.
Claim 4
Dependent Claim
53 words
The method according to claim 1, further comprising the step of: d1) after performing the step d) but before performing the step e), etching areas of the top surface of the substrate which do not include said gate structures of said FETs in order to remove the oxidation mask on the etched areas.
Claim 5
Dependent Claim
28 words
The method according to claim 2, further comprising the step of: g) forming contacts for the source region, the drain region, and the gate structure of each FET.
Claim 6
Dependent Claim
21 words
The method according to claim 4, further comprising the step of: h) forming conductive lines between the contacts of each FET.
Claim 7
Dependent Claim
23 words
The method according to claim 1, wherein the polysilicon layer formed during the step b) is deposited and doped at a same time.
Claim 8
Dependent Claim
22 words
The method according to claim 1, wherein the polysilicon layer formed during the step b) is first deposited and then later doped.
Claim 9
Dependent Claim
23 words
The method according to claim 3, wherein, during the step d1), a nitride spacer is formed on opposite sides of the polysilicon layer.
Claim 10
Dependent Claim
26 words
The method according to claim 8, wherein the etching performed during the step d1) is done to the top surface of the substrate and no further.
Claim 11
Dependent Claim
37 words
The method according to claim 8, wherein the etching performed during the step d1) is done below the top surface of the substrate, thereby forming step region on opposite sides of the gate structures of the FETs.
Claim 12
Independent Claim
151 words
A method of fabricating an integrated circuit semiconductor device having a plurality of field effect transistors (FETs) in and on a silicon substrate with local oxidation of silicon (LOCOS) as field oxide isolating regions between the FETs, the method comprising the steps of: a) forming a gate oxide layer on a top surface of the substrate; b) forming a polysilicon layer on said gate oxide layer; c) etching said gate oxide layer and said polysilicon layer to form gate structures for the FETs; d) surrounding said gate structures with an oxidation mask; e) etching areas of the top surface of the substrate which do not include the gate structures of said FETs such that the substrate is thicker underneath the gate structures for said FETs than it is at other areas of the substrate; and f) forming the LOCOS field oxide isolation regions by growing an oxide layer between the FETs.
Claim 13
Independent Claim
151 words
A method of fabricating an integrated circuit semiconductor device having a plurality of field effect transistors (FETs) in and on a silicon substrate with local oxidation of silicon (LOCOS) as field oxide isolating regions between the FETs, the method comprising the steps of: a) forming a gate oxide layer on a top surface of the substrate; b) forming a polysilicon layer on said gate oxide layer; c) etching said gate oxide layer and said polysilicon layer to form gate structures for the FETs; d) surrounding said gate structures with an oxidation mask; e) etching areas of the top surface of the substrate which do not include the gate structures of said FETs such that the substrate is thicker underneath the gate structures for said FETs than it is at other areas of the substrate; and f) forming the LOCOS field oxide isolation regions by growing an oxide layer between the FETs.
Claim 14
Dependent Claim
20 words
The method according to claim 11, further comprising the step of: g) forming source and drain regions for the FETs.
Claim 15
Dependent Claim
28 words
The method according to claim 12, further comprising the step of: h) forming contacts for the source region, the drain region, and the gate structure of each FET.
Claim 16
Dependent Claim
21 words
The method according to claim 13, further comprising the step of: i) forming conductive lines between the contacts of each FET.
Claim 17
Dependent Claim
23 words
The method according to claim 11, wherein the polysilicon layer formed during the step b) is deposited and doped at a same time.
Claim 18
Dependent Claim
22 words
The method according to claim 11, wherein the polysilicon layer formed during the step b) is first deposited and then later doped.
Claim 19
Dependent Claim
23 words
The method according to claim 11, wherein, during the step e), a nitride spacer is formed on opposite sides of the polysilicon layer.
Claim 20
Dependent Claim
45 words
The method according to claim 17, wherein the etching performed during the step e) forms step regions on opposite sides of the gate structures of the FETs, and wherein the step regions are covered by the corresponding nitride spacer after the step e) is finished.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2000-03-17 | 2000-09-16 | 2001-03-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-17 | 2004-09-16 | 2005-03-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-17 | 2008-09-16 | 2009-03-18 | $7700.00 | Window Closed / Lapsed |