Method for making electrical connections to self-aligned contacts that extends beyond the photo-lithographic resolution limit

Claim 1

A method for fabricating electrical connections to self-aligned source/drain contact areas for field effect transistors comprising the steps of: forming on a semiconductor substrate field oxide regions surrounding and electrically isolating device areas; forming a gate oxide on said device areas; depositing a first polysilicon layer on said device areas and elsewhere on said substrate, said first polysilicon layer being conductively doped; depositing a first insulating layer on said first polysilicon layer; patterning by using a photoresist mask and anisotropic plasma etching said first insulating layer and said first polysilicon layer, thereby forming gate electrodes over said device areas and electrical interconnecting lines over said field oxide regions; forming lightly doped source/drain areas in said device areas adjacent to said gate electrodes by ion implantation; depositing a first sidewall insulating layer; and anisotropically plasma etching said first sidewall insulating layer thereby forming insulating sidewall spacers on sidewalls of said gate electrodes; depositing a conformal second polysilicon layer on said substrate and contacting said device areas; forming self-aligned source/drain contact areas in said device areas adjacent to said sidewall spacers by ion implanting into said second polysilicon layer; forming a refractory metal silicide layer on said second polysilicon layer, thereby forming a polycide layer; depositing a second insulating layer on said silicide layer; coating a photoresist layer on said second insulating layer; patterning said photoresist layer, said patterned photoresist layer having open regions over said gate electrodes and lying between said source/drain areas in each said field effect transistor, and also having open regions over said field oxide regions, said open regions having the minimum feature size achievable by said photoresist layer; anisotropically plasma etching and removing said second insulating layer, and etching partially into said polycide layer in said open regions and thereby forming recesses having vertical sidewalls; removing said photoresist layer; depositing a second sidewall insulating layer and anisotropically etching back thereby forming second sidewall spacers on said sidewalls in said recesses thereby reducing said minimum feature size of said photoresist by twice the width of said second sidewall spacers; anisotropic plasma etching and removing said remaining polycide layer in said recesses between said second sidewall spacers, and thereby completing said electrical connections to said self-aligned source/drain contact areas.

Claim 2

A method for fabricating electrical connections to self-aligned source/drain contact areas for field effect transistors comprising the steps of: forming on a semiconductor substrate field oxide regions surrounding and electrically isolating device areas; forming a gate oxide on said device areas; depositing a first polysilicon layer on said device areas and elsewhere on said substrate, said first polysilicon layer being conductively doped; depositing a first insulating layer on said first polysilicon layer; patterning by using a photoresist mask and anisotropic plasma etching said first insulating layer and said first polysilicon layer, thereby forming gate electrodes over said device areas and electrical interconnecting lines over said field oxide regions; forming lightly doped source/drain areas in said device areas adjacent to said gate electrodes by ion implantation; depositing a first sidewall insulating layer; and anisotropically plasma etching said first sidewall insulating layer thereby forming insulating sidewall spacers on sidewalls of said gate electrodes; depositing a conformal second polysilicon layer on said substrate and contacting said device areas; forming self-aligned source/drain contact areas in said device areas adjacent to said sidewall spacers by ion implanting into said second polysilicon layer; forming a refractory metal silicide layer on said second polysilicon layer, thereby forming a polycide layer; depositing a second insulating layer on said silicide layer; coating a photoresist layer on said second insulating layer; patterning said photoresist layer, said patterned photoresist layer having open regions over said gate electrodes and lying between said source/drain areas in each said field effect transistor, and also having open regions over said field oxide regions, said open regions having the minimum feature size achievable by said photoresist layer; anisotropically plasma etching and removing said second insulating layer, and etching partially into said polycide layer in said open regions and thereby forming recesses having vertical sidewalls; removing said photoresist layer; depositing a second sidewall insulating layer and anisotropically etching back thereby forming second sidewall spacers on said sidewalls in said recesses thereby reducing said minimum feature size of said photoresist by twice the width of said second sidewall spacers; anisotropic plasma etching and removing said remaining polycide layer in said recesses between said second sidewall spacers, and thereby completing said electrical connections to said self-aligned source/drain contact areas.