Method of making flash EEPROM cell

Claim 1

A method of making a flash EEPROM cell, comprising the steps of: sequentially forming a pad oxide film and a nitride film on a silicon substrate; patterning said nitride film and said pad oxide film to open a portion of said silicon substrate and form an etched surface of said nitride film; forming an oxide film with an exposed portion in a portion of said silicon substrate by means of an oxidation process using said patterned nitride film as an oxidation preventing layer; etching the exposed portion of said oxide film by means of an etching process using said patterned nitride film as an etching mask to expose a portion of said silicon substrate, thereby forming a first and second residual oxide film, both with an etched surface, below said patterned nitride film; forming a tunnel oxide film on said exposed silicon substrate; forming a first floating gate at the etched surface of said patterned nitride film and said first residual oxide film, and then forming a second floating gate at the etched surface of said patterned nitride film and said second residual oxide film; removing said patterned nitride film, and then forming source and drain regions by means of a self-aligned ion implantation method using said first and second floating gates and said first and second residual oxide films as masks, thereby leaving the tunnel oxide and pad oxide partially exposed; removing said first and second residual oxide films and removing said exposed pad oxide film and said exposed tunnel oxide film; forming a select channel region in said silicon substrate by an ion implantation process for controlling a threshold voltage; and sequentially forming an interpoly oxide film and a control gate on the resulting structure after forming said select channel region.

Claim 2

A method of making a flash EEPROM cell, comprising the steps of: sequentially forming a pad oxide film and a nitride film on a silicon substrate; patterning said nitride film and said pad oxide film to open a portion of said silicon substrate and form an etched surface of said nitride film; forming an oxide film with an exposed portion in a portion of said silicon substrate by means of an oxidation process using said patterned nitride film as an oxidation preventing layer; etching the exposed portion of said oxide film by means of an etching process using said patterned nitride film as an etching mask to expose a portion of said silicon substrate, thereby forming a first and second residual oxide film, both with an etched surface, below said patterned nitride film; forming a tunnel oxide film on said exposed silicon substrate; forming a first floating gate at the etched surface of said patterned nitride film and said first residual oxide film, and then forming a second floating gate at the etched surface of said patterned nitride film and said second residual oxide film; removing said patterned nitride film, and then forming source and drain regions by means of a self-aligned ion implantation method using said first and second floating gates and said first and second residual oxide films as masks, thereby leaving the tunnel oxide and pad oxide partially exposed; removing said first and second residual oxide films and removing said exposed pad oxide film and said exposed tunnel oxide film; forming a select channel region in said silicon substrate by an ion implantation process for controlling a threshold voltage; and sequentially forming an interpoly oxide film and a control gate on the resulting structure after forming said select channel region.