US5610926A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method & circuit for testing ic logic circuits
Assignee: Texas Instruments Inc
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Filing: 1995-09-26
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Granted: 1997-03-11
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Expires: 2015-09-26
Abstract
Abstract Integrated logic circuit and method of functionally testing the integrated logic circuit, wherein the integrated logic circuit includes storage elements configurable as at least a part of a scan path in which a feedback from elements in the path to a previous element is provided. The method of functionally testing the integrated logic circuit effectively provides a simple exercising of the integrated logic circuit by clocking the elements in the scan path. In a specific aspect, the feedback arrangement provides a linear feedback shift register with exclusive-OR gating.
Inventors
- 👤 Arthur Marris
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 20:38
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318544; G01R31/318547
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
104 words
A method of testing an IC logic chip having storage elements configurable as part of a scan path, without applying an external test data signal, comprising the steps of: (a) providing a feedback from elements in the scan path to a previous element in the scan path to internally produce a pseudo random binary testing sequence for an internal test data signal input of the scan path; (b) applying a scan clock to reconfigure the elements into the scan path; and (c) monitoring an output of the scan path to assess the response of the IC logic chip to the internal test data signal.
Claim 2
Independent Claim
104 words
A method of testing an IC logic chip having storage elements configurable as part of a scan path, without applying an external test data signal, comprising the steps of: (a) providing a feedback from elements in the scan path to a previous element in the scan path to internally produce a pseudo random binary testing sequence for an internal test data signal input of the scan path; (b) applying a scan clock to reconfigure the elements into the scan path; and (c) monitoring an output of the scan path to assess the response of the IC logic chip to the internal test data signal.
Claim 3
Dependent Claim
100 words
An IC logic chip testable without applying an external test data signal, comprising: storage elements configurable as a scan path having an input for an internal test data signal and an output, a feedback from elements in the path to a previous element in the scan path to produce a pseudo random binary testing sequence for the input of the scan path, a scan clock for reconfiguring the elements into the scan path, and a monitor circuit responsive to the output of the scan path for assessing the response of the IC logic chip to the internal test data signal.
Claim 4
Dependent Claim
100 words
An IC logic chip testable without applying an external test data signal, comprising: storage elements configurable as a scan path having an input for an internal test data signal and an output, a feedback from elements in the path to a previous element in the scan path to produce a pseudo random binary testing sequence for the input of the scan path, a scan clock for reconfiguring the elements into the scan path, and a monitor circuit responsive to the output of the scan path for assessing the response of the IC logic chip to the internal test data signal.
Claim 5
Dependent Claim
19 words
An IC logic chip as claimed in claim 2 wherein the feedback arrangement provides a linear feedback shift register.
Claim 6
Dependent Claim
16 words
An IC logic chip as claimed in claim 3 wherein the feedback path includes Exclusive-OR gating.
Claim 7
Dependent Claim
23 words
An IC logic chip as claimed in claim 3 wherein at least one of the elements is arranged for a non-zero initial value.
Claim 8
Dependent Claim
22 words
An IC logic chip as claimed in claim 2 wherein at least part of the feedback path is integrated within a device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-10 | 2000-09-09 | 2001-03-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-10 | 2004-09-09 | 2005-03-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-10 | 2008-09-09 | 2009-03-11 | $7700.00 | Window Closed / Lapsed |