Semiconductor memory device and fabrication process thereof

Claim 1

A semiconductor memory device, comprising: a semiconductor substrate defined with a peripheral circuit region for carrying peripheral circuits and a memory cell array region for carrying a memory cell array; a first well of a first conductivity type formed in said semiconductor substrate in correspondence to said memory cell array region, said first well having a surface at a first level; a second well of a second, opposite conductivity type formed in said first well, said second well having a surface at a second level lower than said first level, said surface of said second well being separated from said surface of said first well by a stepped boundary; a memory cell transistor provided on said second well; a memory cell capacitor provided on the surface of said second well so as to extend in an upward direction therefrom; an insulating film provided on said memory cell array so as to cover said memory cell transistor and said memory cell capacitor; a conductive region provided on said semiconductor substrate so as to extend from the surface of said second well to the surface of said first well across said stepped boundary; a contact hole provided on said insulating film in correspondence to said first well so as to expose said conductive region; and an electrode filling said contact hole to establish an electrical contact with said conductive region.