US5504708A
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Flash EEPROM array with P-tank insulated from substrate by deep N-tank
Assignee: Texas Instruments Inc
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Filing: 1995-01-05
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Granted: 1996-04-02
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Expires: 2015-01-05
Abstract
Abstract In accordance with one embodiment of the invention, a nonvolatile memory array is encased in a P-tank, and the P-tank encased in a deep N-tank, the two tanks separating the memory array from the substrate and from the other circuitry of the integrated memory circuit. The deep N-tank allows application of a negative voltage of perhaps -8 V to the P-tank encasing the memory array. Application of that negative voltage permits the cells of the memory array to be programmed with voltage pulses having a peak value of about +10 V, rather than the +18 V peak value of prior-art memory arrays. Because the external circuitry, such as the wordline driver circuit, need drive the wordlines at +10 V rather than +18 V, the invention permits construction of that external circuitry using thinner gate insulators and space-saving shorter dimensions.
Inventors
- 👤 Giovanni Santin
- 👤 Giovanni Naso
- 👤 Sebastiano D'Arrigo
- 👤 Michael C. Smayling
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:26
CPC Classifications
H; H10; H10B; H10B69/00; H10B41/00; H10B41/30
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
91 words
A nonvolatile, floating-gate memory, comprising: a semiconductor body having doping of a first conductivity-type; a first diffusion region in said semiconductor body, said first diffusion region having doping primarily of a second conductivity-type opposite said first conductivity-type; a second diffusion region in said first diffusion region and in said semiconductor body, said second diffusion region having doping primarily of said first conductivity-type; an array of floating-gate memory cells in and on said second diffusion region; and wordline driver circuitry in and on said semiconductor body outside of said first diffusion region.
Claim 2
Dependent Claim
91 words
A nonvolatile, floating-gate memory, comprising: a semiconductor body having doping of a first conductivity-type; a first diffusion region in said semiconductor body, said first diffusion region having doping primarily of a second conductivity-type opposite said first conductivity-type; a second diffusion region in said first diffusion region and in said semiconductor body, said second diffusion region having doping primarily of said first conductivity-type; an array of floating-gate memory cells in and on said second diffusion region; and wordline driver circuitry in and on said semiconductor body outside of said first diffusion region.
Claim 3
Dependent Claim
35 words
The floating-gate memory of claim 1, wherein said semiconductor body is silicon of P conductivity-type, said first diffusion region is primarily of N conductivity-type and said second diffusion region is primarily of P conductivity type.
Claim 4
Dependent Claim
26 words
The floating-gate memory of claim 1, wherein said first diffusion region is connected to a non-negative potential with respect to the potential of said semiconductor body.
Claim 5
Dependent Claim
28 words
The floating-gate memory of claim 1, wherein said floating-gate memory has a primary power supply and wherein said first diffusion region is connected to said primary power supply.
Claim 6
Dependent Claim
33 words
The floating-gate memory of claim 1, wherein during programming operation, said second diffusion region is connected to a source of potential that is negative with respect to the potential of said semiconductor body.
Claim 7
Dependent Claim
38 words
The floating-gate memory of claim 1, wherein during programming operation, said second diffusion region is connected to a charge pump voltage supply having an output voltage that is negative with respect to the voltage of said semiconductor body.
Claim 8
Dependent Claim
19 words
The floating-gate memory of claim 1, wherein Fowler-Nordheim tunnelling is used to program said floating gates of memory cells.
Claim 9
Dependent Claim
26 words
The floating-gate memory of claim 1, wherein said wordline driver circuitry operates at a maximum voltage less than the voltage required to program said floating-gate memory.
Claim 10
Dependent Claim
203 words
A nonvolatile, floating-gate memory, comprising: a semiconductor body having doping of a first conductivity-type; a first diffusion region in said semiconductor body, said first diffusion region having doping primarily of a second conductivity-type opposite said first conductivity-type; a second diffusion region in said first diffusion region and in said semiconductor body, said second diffusion region having doping primarily of said first conductivity-type; an array of floating-gate memory cells in and on said P-tank diffusion; and wordline driver circuitry in and on said semiconductor body outside of said first diffusion region; wherein said semiconductor body is silicon of P conductivity-type, said first diffusion region is primarily of N conductivity-type and said second diffusion region is primarily of P conductivity type; wherein said first diffusion region is connected to a non-negative potential with respect to the potential of said semiconductor body; wherein during programming operation, said second diffusion region is connected to a source of potential that is negative with respect to the potential of said semiconductor body; wherein Fowler-Nordheim tunnelling is used to program said floating gates of memory cells; and wherein said wordline driver circuitry is constructed to operate at a maximum voltage less than the voltage required to program said floating-gate memory.
Claim 11
Dependent Claim
203 words
A nonvolatile, floating-gate memory, comprising: a semiconductor body having doping of a first conductivity-type; a first diffusion region in said semiconductor body, said first diffusion region having doping primarily of a second conductivity-type opposite said first conductivity-type; a second diffusion region in said first diffusion region and in said semiconductor body, said second diffusion region having doping primarily of said first conductivity-type; an array of floating-gate memory cells in and on said P-tank diffusion; and wordline driver circuitry in and on said semiconductor body outside of said first diffusion region; wherein said semiconductor body is silicon of P conductivity-type, said first diffusion region is primarily of N conductivity-type and said second diffusion region is primarily of P conductivity type; wherein said first diffusion region is connected to a non-negative potential with respect to the potential of said semiconductor body; wherein during programming operation, said second diffusion region is connected to a source of potential that is negative with respect to the potential of said semiconductor body; wherein Fowler-Nordheim tunnelling is used to program said floating gates of memory cells; and wherein said wordline driver circuitry is constructed to operate at a maximum voltage less than the voltage required to program said floating-gate memory.
Claim 12
Independent Claim
138 words
A method for programming a nonvolatile floating-gate memory array, said memory array including a semiconductor body having doping of a first conductivity-type; including a first diffusion region in said semiconductor body, said first diffusion region having doping primarily of a second conductivity-type opposite said first conductivity-type; including a second diffusion region in said first diffusion region and in said semiconductor body, said second diffusion region having doping primarily of said first conductivity-type; said array having memory cells in and on said P-tank diffusion and having wordline driver circuitry in and on said semiconductor body outside of said first diffusion region; said method comprising: applying a non-negative voltage to said first diffusion region; applying a negative voltage to said second diffusion region; causing said wordline driver circuitry to apply a positive voltage to selected wordlines of said memory array.
Claim 13
Independent Claim
138 words
A method for programming a nonvolatile floating-gate memory array, said memory array including a semiconductor body having doping of a first conductivity-type; including a first diffusion region in said semiconductor body, said first diffusion region having doping primarily of a second conductivity-type opposite said first conductivity-type; including a second diffusion region in said first diffusion region and in said semiconductor body, said second diffusion region having doping primarily of said first conductivity-type; said array having memory cells in and on said P-tank diffusion and having wordline driver circuitry in and on said semiconductor body outside of said first diffusion region; said method comprising: applying a non-negative voltage to said first diffusion region; applying a negative voltage to said second diffusion region; causing said wordline driver circuitry to apply a positive voltage to selected wordlines of said memory array.
Claim 14
Dependent Claim
26 words
The method according to claim 10, wherein said wordline driver circuitry operates at a maximum voltage less than the voltage required to program said floating-gate memory.
Claim 15
Dependent Claim
35 words
The method according to claim 10, wherein said semiconductor body is silicon of P conductivity-type, said first diffusion region is primarily of N conductivity-type and said second diffusion region is primarily of P conductivity type.
References Cited (Backward Citations)
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Cited
US5309402A
Cited
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