Controlled tracking of oscillators in a circuit with multiple frequency sensitive elements

Claim 2

An oscillator circuit comprising: a master phase-locked loop (PLL) circuit responsive to a first reference frequency signal, the master PLL circuit comprising: a first oscillator having an input responsive to an oscillator control signal for generating as output a first clock signal; a first divider having an input coupled to an output of the first oscillator for dividing a frequency of the first clock signal by a first divide constant and generating as output a first frequency divided signal; a first phase detector receiving as input the first reference frequency signal and the first frequency divided signal and generating a first phase detector output signal; a first loop filter coupled to an output of the first phase detector for filtering the first phase detector output signal and for generating as output the oscillator control signal that is coupled to an input of the first oscillator; a slave PLL circuit responsive to a second reference frequency signal, the slave PLL circuit comprising: a second oscillator that is substantially identical to the first oscillator and having an input responsive to a tracking control signal for generating as output a second clock signal; a second divider having an input coupled to an output of the second oscillator for dividing a frequency of the second clock signal by a second divide constant and generating as output a second frequency divided signal; a second phase detector receiving as input the second reference frequency signal and the second frequency divided signal and generating a second phase detector output signal; a second loop filter coupled to an output of the second phase detector for filtering the second phase detector output signal and for generating as output a second filtered signal that is coupled to an input of the second oscillator; and a tracking control circuit coupled to the master PLL circuit and the slave PLL circuit to receive as input the oscillator control signal, and a tracking information signal, to generate the tracking control signal based thereon.

Claim 3

The oscillator circuit of claim 1, wherein the tracking information signal includes tracking information determined by multiplying the oscillator control signal by a ratio of the second divide constant to the first divide constant and by a ratio of a frequency of the second reference frequency signal to a frequency of the first reference frequency signal.

Claim 4

The oscillator circuit of claim 1, wherein the first oscillator and the second oscillator are current controlled oscillators, and wherein the oscillator control signal and the tracking control signal are current signals.

Claim 5

A processor system, comprising an oscillator circuit comprising: a master phase-locked loop (PLL) circuit responsive to a first reference frequency signal, the master PLL circuit comprising: a first oscillator having an input responsive to an oscillator control signal for generating as output a first clock signal; a first divider having an input coupled to an output of the first oscillator for dividing a frequency of the first clock signal by a first divide constant and generating as output a first frequency divided signal; a first phase detector receiving as input the first reference frequency signal and the first frequency divided signal and generating a first phase detector output signal; a first loop filter coupled to an output of the first phase detector for filtering the first phase detector output signal and for generating as output the oscillator control signal that is coupled to an input of the first oscillator; a slave PLL circuit responsive to a second reference frequency signal, the slave PLL circuit comprising: a second oscillator that is substantially identical to the first oscillator and having an input responsive to a tracking control signal for generating as output a second clock signal; a second divider having an input coupled to an output of the second oscillator for dividing a frequency of the second clock signal by a second divide constant and generating as output a second frequency divided signal; a second phase detector receiving as input the second reference frequency signal and the second frequency divided signal and generating a second phase detector output signal; a second loop filter coupled to an output of the second phase detector for filtering the second phase detector output signal and for generating as output a second filtered signal that is coupled to an input of the second oscillator; and a tracking control circuit coupled to the master PLL circuit and the slave PLL circuit to receive as input the oscillator control signal, and a tracking information signal to generate the tracking control signal based thereon.

Claim 6

A processor system, comprising an oscillator circuit comprising: a master phase-locked loop (PLL) circuit responsive to a first reference frequency signal, the master PLL circuit comprising: a first oscillator having an input responsive to an oscillator control signal for generating as output a first clock signal; a first divider having an input coupled to an output of the first oscillator for dividing a frequency of the first clock signal by a first divide constant and generating as output a first frequency divided signal; a first phase detector receiving as input the first reference frequency signal and the first frequency divided signal and generating a first phase detector output signal; a first loop filter coupled to an output of the first phase detector for filtering the first phase detector output signal and for generating as output the oscillator control signal that is coupled to an input of the first oscillator; a slave PLL circuit responsive to a second reference frequency signal, the slave PLL circuit comprising: a second oscillator that is substantially identical to the first oscillator and having an input responsive to a tracking control signal for generating as output a second clock signal; a second divider having an input coupled to an output of the second oscillator for dividing a frequency of the second clock signal by a second divide constant and generating as output a second frequency divided signal; a second phase detector receiving as input the second reference frequency signal and the second frequency divided signal and generating a second phase detector output signal; a second loop filter coupled to an output of the second phase detector for filtering the second phase detector output signal and for generating as output a second filtered signal that is coupled to an input of the second oscillator; and a tracking control circuit coupled to the master PLL circuit and the slave PLL circuit to receive as input the oscillator control signal, and a tracking information signal to generate the tracking control signal based thereon.

Claim 7

The processor system of claim 4, and further comprising a system control circuit coupled to the tracking control circuit and coupled to the slave PLL circuit for receiving the second clock signal therefrom, the system control circuit for generating the tracking information signal by multiplying the oscillator control signal by a ratio of the second divide constant to the first divide constant and by a ratio of a frequency of the second reference frequency signal to a frequency of the first reference frequency signal.

Claim 8

The processor system of claim 5, wherein the system control circuit generates an ON/OFF control signal that is coupled to the slave PLL circuit for enabling and disabling the slave PLL circuit.

Claim 9

A selective call receiver, comprising a processor system having an oscillator circuit comprising: a master phase-locked loop (PLL) circuit responsive to a first reference frequency signal, the master PLL circuit comprising: a first oscillator having an input responsive to an oscillator control signal for generating as output a first clock signal; a first divider having an input coupled to an output of the first oscillator for dividing a frequency of the first clock signal by a first divide constant and generating as output a first frequency divided signal; a first phase detector receiving as input the first reference frequency signal and the first frequency divided signal and generating a first phase detector output signal; a first loop filter coupled to an output of the first phase detector for filtering the first phase detector output signal and for generating as output the oscillator control signal that is coupled to an input of the first oscillator; a slave PLL circuit responsive to a second reference frequency signal, the slave PLL circuit comprising: a second oscillator that is substantially identical to the first oscillator and having an input responsive to a tracking control signal for generating as output a second clock signal; a second divider having an input coupled to an output of the second oscillator for dividing a frequency of the second clock signal by a second divide constant and generating as output a second frequency divided signal; a second phase detector receiving as input the second reference frequency signal and the second frequency divided signal and generating a second phase detector output signal; a second loop filter coupled to an output of the second phase detector for filtering the second phase detector output signal and for generating as output a second filtered signal that is coupled to an input of the second oscillator; and a tracking control circuit coupled to the master PLL circuit and the slave PLL circuit to receive as input the oscillator control signal, and a tracking information signal to generate the tracking control signal based thereon.

Claim 10

A selective call receiver, comprising a processor system having an oscillator circuit comprising: a master phase-locked loop (PLL) circuit responsive to a first reference frequency signal, the master PLL circuit comprising: a first oscillator having an input responsive to an oscillator control signal for generating as output a first clock signal; a first divider having an input coupled to an output of the first oscillator for dividing a frequency of the first clock signal by a first divide constant and generating as output a first frequency divided signal; a first phase detector receiving as input the first reference frequency signal and the first frequency divided signal and generating a first phase detector output signal; a first loop filter coupled to an output of the first phase detector for filtering the first phase detector output signal and for generating as output the oscillator control signal that is coupled to an input of the first oscillator; a slave PLL circuit responsive to a second reference frequency signal, the slave PLL circuit comprising: a second oscillator that is substantially identical to the first oscillator and having an input responsive to a tracking control signal for generating as output a second clock signal; a second divider having an input coupled to an output of the second oscillator for dividing a frequency of the second clock signal by a second divide constant and generating as output a second frequency divided signal; a second phase detector receiving as input the second reference frequency signal and the second frequency divided signal and generating a second phase detector output signal; a second loop filter coupled to an output of the second phase detector for filtering the second phase detector output signal and for generating as output a second filtered signal that is coupled to an input of the second oscillator; and a tracking control circuit coupled to the master PLL circuit and the slave PLL circuit to receive as input the oscillator control signal, and a tracking information signal to generate the tracking control signal based thereon.

Claim 11

The selective call receiver of claim 7, wherein the processor system further comprises a system control circuit coupled to the tracking control circuit and coupled to the slave PLL circuit for receiving the second clock signal therefrom, the system control circuit for generating the tracking information signal by multiplying the oscillator control signal by a ratio of the second divide constant to the first divide constant and by a ratio of a frequency of the second reference frequency signal to a frequency of the first reference frequency signal.

Claim 12

The selective call receiver of claim 8, wherein the system control circuit generates an ON/OFF control signal that is coupled to the slave PLL circuit for enabling and disabling the slave PLL circuit.