Semiconductor integrated circuit device with elements isolated by trenches

Claim 2

A semiconductor integrated circuit device comprising: a semiconductor substrate; a plurality of trenches formed in parallel at the main surface of said semiconductor substrate; a plurality of projecting portions formed between said trenches; a first group of devices each formed at a bottom of a corresponding one of said trenches; and a second group of devices each formed at a corresponding one of said projecting portions, each of said second group of devices being separated from said first group of devices in a direction of depth of said trenches, thereby insulated from each of said first group of devices.

Claim 3

A semiconductor integrated circuit device according to claim 1, wherein said semiconductor substrate contains a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed in the surface region of the first-conductivity-type semiconductor substrate, and said trenches are formed in said well region.

Claim 4

A semiconductor integrated circuit device according to claim 2, further comprising an inversion prevention impurity diffusion region of the second conductivity type which is formed in the surface region of said well region and whose impurity concentration is higher than that of said well region.

Claim 5

A semiconductor integrated circuit device according to claim 1, further comprising inversion prevention spacers formed on the sidewall portions of said trenches, for preventing the sidewall portions of said trenches from being inverted, thereby preventing said first and second groups of devices from being electrically connected to each other.

Claim 6

A semiconductor integrated circuit device according to claim 4, said spacers are insulting layers formed on said sidewall portions of said trenches.

Claim 7

A semiconductor integrated circuit device comprising: a semiconductor substrate; a plurality of trenches formed in parallel at the surface of said semiconductor substrate; a plurality of projecting portions formed between said trenches; first active regions of a first group of cell transistors formed at bottoms of said trenches in the semiconductor substrate; second active regions of a second group of cell transistors formed on each of said projecting portions; first floating gates of said first group of cell transistors, each provided above a portion between said first active regions formed at the bottoms of said trenches; second floating gates of said second group of cell transistors, each provided above a portion between said second active regions formed on said projecting portions; and a control gate extended over said first and second floating gates in the direction that crosses said trenches, said control gate being shared by the first and second groups of cell transistors, wherein the first group of cell transistors formed at the bottoms of each of said trenches are electrically isolated from the second group of cell transistors formed on the projecting portion between said trenches by separating the former from the latter in the direction of depth of said trenches.

Claim 8

A semiconductor integrated circuit device comprising: a semiconductor substrate; a plurality of trenches formed in parallel at the surface of said semiconductor substrate; a plurality of projecting portions formed between said trenches; first active regions of a first group of cell transistors formed at bottoms of said trenches in the semiconductor substrate; second active regions of a second group of cell transistors formed on each of said projecting portions; first floating gates of said first group of cell transistors, each provided above a portion between said first active regions formed at the bottoms of said trenches; second floating gates of said second group of cell transistors, each provided above a portion between said second active regions formed on said projecting portions; and a control gate extended over said first and second floating gates in the direction that crosses said trenches, said control gate being shared by the first and second groups of cell transistors, wherein the first group of cell transistors formed at the bottoms of each of said trenches are electrically isolated from the second group of cell transistors formed on the projecting portion between said trenches by separating the former from the latter in the direction of depth of said trenches.

Claim 9

A semiconductor integrated circuit device according to claim 6, wherein said semiconductor substrate contains a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed in the surface region of the first-conductivity-type semiconductor substrate, and said trenches are formed in said well region.

Claim 10

A semiconductor integrated circuit device according to claim 7, further comprising an inversion prevention impurity diffusion region of the second conductivity type which is formed in said well region and whose impurity concentration is higher than that of said well region.

Claim 11

A semiconductor integrated circuit device according to claim 6, further comprising inversion prevention spacers formed on the sidewall portions of said trenches, for preventing the sidewall portions of said trenches from being inverted when potentials of said first floating gates increase, and thereby preventing channels from being formed between said first and second groups of cell transistors.

Claim 12

A semiconductor integrated circuit device according to claim 9, wherein said spacers are insulting layers formed on said sidewall portions of said trenches.

Claim 13

A semiconductor integrated circuit device comprising: a semiconductor substrate of a first conductivity type; a well region of a second conductivity type formed at a surface of said semiconductor substrate; a plurality of trenches formed in parallel in said well region; a plurality of projecting portions formed between said trenches; first drain and source regions of a first group of cell transistors, which have the first conductivity type and are formed at the bottoms of said trenches; second drain and source regions of a second group of cell transistors, which have the first conductivity type and are formed on said projecting portions; first gate insulating films of said first group of cell transistors, each of which is formed above a portion between said first drain and source regions at the bottom of each of said trenches; second gate insulating films of said second group of cell transistors, each of which is formed above a portion between said second drain and source regions formed on each projecting portion; first floating gates of said first group of cell transistors, each of which is formed on a corresponding one of said first gate insulating films; second floating gates of said second group of cell transistors, each of which is formed on a corresponding one of said second gate insulting films; third gate insulating films of said first group of cell transistors, each of which is formed on a surface of a corresponding one of said first floating gates; fourth gate insulating films of said second group of cell transistors, each of which is formed on a surface of a corresponding one of said second floating gates; and a plurality of control gates formed in parallel on said third and fourth gate insulating films and extended over said said first and second floating gates in the direction perpendicular to said trenches, each of said control gates being shared by a corresponding one of said first groups of cell transistors and a corresponding one of said second groups of cell transistors, wherein the first group of cell transistors, each of which is formed at the bottom of a corresponding one of said trenches are electrically isolated from the second group of cell transistors, each of which is formed on a corresponding one of said projecting portions between said trenches by separating the former from the latter in the direction of depth of said trenches, and NAND type E 2 PROM cells where current paths of said first and second groups of cell transistors are alternately connected in series are formed in the direction in which said trenches extend at the bottoms of said trenches and on projecting portions between said trenches.

Claim 14

A semiconductor integrated circuit device comprising: a semiconductor substrate of a first conductivity type; a well region of a second conductivity type formed at a surface of said semiconductor substrate; a plurality of trenches formed in parallel in said well region; a plurality of projecting portions formed between said trenches; first drain and source regions of a first group of cell transistors, which have the first conductivity type and are formed at the bottoms of said trenches; second drain and source regions of a second group of cell transistors, which have the first conductivity type and are formed on said projecting portions; first gate insulating films of said first group of cell transistors, each of which is formed above a portion between said first drain and source regions at the bottom of each of said trenches; second gate insulating films of said second group of cell transistors, each of which is formed above a portion between said second drain and source regions formed on each projecting portion; first floating gates of said first group of cell transistors, each of which is formed on a corresponding one of said first gate insulating films; second floating gates of said second group of cell transistors, each of which is formed on a corresponding one of said second gate insulting films; third gate insulating films of said first group of cell transistors, each of which is formed on a surface of a corresponding one of said first floating gates; fourth gate insulating films of said second group of cell transistors, each of which is formed on a surface of a corresponding one of said second floating gates; and a plurality of control gates formed in parallel on said third and fourth gate insulating films and extended over said said first and second floating gates in the direction perpendicular to said trenches, each of said control gates being shared by a corresponding one of said first groups of cell transistors and a corresponding one of said second groups of cell transistors, wherein the first group of cell transistors, each of which is formed at the bottom of a corresponding one of said trenches are electrically isolated from the second group of cell transistors, each of which is formed on a corresponding one of said projecting portions between said trenches by separating the former from the latter in the direction of depth of said trenches, and NAND type E 2 PROM cells where current paths of said first and second groups of cell transistors are alternately connected in series are formed in the direction in which said trenches extend at the bottoms of said trenches and on projecting portions between said trenches.

Claim 15

A semiconductor integrated circuit device according to claim 11, further comprising an inversion prevention impurity diffusion region of the second conductivity type which is formed in said well region and whose impurity concentration is higher than that of said well region.

Claim 16

A semiconductor integrated circuit device according to claim 11, further comprising inversion prevention spacers formed on the sidewall portions of said trenches, for preventing sidewall portions of said trenches from being inverted when potentials of said first floating gates increase, and thereby preventing channel sections of selected cell transistors and channel sections of unselected cell transistors being electrically connected.

Claim 17

A semiconductor integrated circuit device according to claim 13, wherein said spacers are insulating layers formed on said sidewall portions of said trenches.

Claim 18

A semiconductor integrated circuit device according to claim 11, further comprising an interlayer insulating film formed on said control gate and said semiconductor substrate, and bit lines formed in the same direction that said trenches extend on said interlayer insulating film on the bottom of each of said trenches and on each projecting portion between said trenches.

Claim 19

A semiconductor integrated circuit device according to claim 15, further comprising first and second cell select transistors for selecting said first and second groups of cell transistors which are connected in series, the drains of the first cell select transistors being connected to said bit lines and the sources of the second cell select transistors being grounded.

Claim 20

A semiconductor integrated circuit device comprising: a semiconductor substrate of a first conductivity type; a plurality of trenches formed in parallel in a first direction at the surface of said semiconductor substrate; a plurality of projecting portions formed between said trenches; first drain and source regions of a first group of cell transistors, which have a second conductivity type and are formed at the bottoms of said trenches; second drain and source regions of a second group of cell transistors, which have the second conductivity type and are formed on said projecting portions; first gate insulating films of said first group of cell transistors, each of which is formed above a portion between said first drain and source regions at the bottom of a corresponding one of said trenches second gate insulating films of said second group of cell transistors, each of which is formed above a portion between said second drain and source regions on corresponding projecting portions; first floating gates of said first group of cell transistors, each of which is formed on a corresponding one of said first gate insulating films; second floating gates of said second group of cell transistors, each of which is formed on a corresponding one of said second gate insulating films; third floating gates of said first group of cell transistors, each of which is formed on a surface of a corresponding one of said first floating gates; fourth floating gates of said second group of cell transistors, each of which is formed on a surface of corresponding one of said second floating gates; a plurality of control gates formed in parallel on said third and fourth gate insulating films and extended over said first and second floating gates in a second direction perpendicular to said first direction, each of said control gates being shared by a corresponding one of said first group of cell transistors and a corresponding one of said second group of cell transistors; an interlayer insulating film formed on the resultant structure, with contact holes made in the positions on said interlayer insulating film above and corresponding to said drain and source regions; source lines formed in said second direction on said interlayer insulating film and connected to said source regions via the contact holes made above said source regions; and bit lines formed in said first direction on said interlayer insulating film and electrically isolated from said source lines and connected to said drain regions via the contact holes made above said drain regions, wherein the first group of cell transistors each of which is formed at the bottom of a corresponding one of said trenches are electrically isolated from the second group of cell transistors each of which is formed on a corresponding one of said projecting portions by separating the former from the latter in the direction of depth of said trenches, and NOR type EE 2 PROM cells are formed at the bottoms of said trenches and on the projecting portions between said trenches.

Claim 21

A semiconductor integrated circuit device comprising: a semiconductor substrate of a first conductivity type; a plurality of trenches formed in parallel in a first direction at the surface of said semiconductor substrate; a plurality of projecting portions formed between said trenches; first drain and source regions of a first group of cell transistors, which have a second conductivity type and are formed at the bottoms of said trenches; second drain and source regions of a second group of cell transistors, which have the second conductivity type and are formed on said projecting portions; first gate insulating films of said first group of cell transistors, each of which is formed above a portion between said first drain and source regions at the bottom of a corresponding one of said trenches second gate insulating films of said second group of cell transistors, each of which is formed above a portion between said second drain and source regions on corresponding projecting portions; first floating gates of said first group of cell transistors, each of which is formed on a corresponding one of said first gate insulating films; second floating gates of said second group of cell transistors, each of which is formed on a corresponding one of said second gate insulating films; third floating gates of said first group of cell transistors, each of which is formed on a surface of a corresponding one of said first floating gates; fourth floating gates of said second group of cell transistors, each of which is formed on a surface of corresponding one of said second floating gates; a plurality of control gates formed in parallel on said third and fourth gate insulating films and extended over said first and second floating gates in a second direction perpendicular to said first direction, each of said control gates being shared by a corresponding one of said first group of cell transistors and a corresponding one of said second group of cell transistors; an interlayer insulating film formed on the resultant structure, with contact holes made in the positions on said interlayer insulating film above and corresponding to said drain and source regions; source lines formed in said second direction on said interlayer insulating film and connected to said source regions via the contact holes made above said source regions; and bit lines formed in said first direction on said interlayer insulating film and electrically isolated from said source lines and connected to said drain regions via the contact holes made above said drain regions, wherein the first group of cell transistors each of which is formed at the bottom of a corresponding one of said trenches are electrically isolated from the second group of cell transistors each of which is formed on a corresponding one of said projecting portions by separating the former from the latter in the direction of depth of said trenches, and NOR type EE 2 PROM cells are formed at the bottoms of said trenches and on the projecting portions between said trenches.

Claim 22

A semiconductor integrated circuit device according to claim 17, further comprising an inversion prevention impurity diffusion region of the first conductivity type which is formed in the surface region of said semiconductor substrate and whose impurity concentration is higher than that of said semiconductor substrate.

Claim 23

A semiconductor integrated circuit device according to claim 18, further comprising a low-concentration impurity diffusion region for alleviating electric fields which is inserted between said source and drain regions and said inversion prevention impurity diffusion region.

Claim 24

A semiconductor integrated circuit device according to claim 17, further comprising inversion prevention spacers formed on the sidewall portions of said trenches, for preventing the sidewall portions of said trenches from being inverted when potentials of said first floating gates of said first group of cell transistors increase, and thereby preventing channel sections of selected cell transistors and channel sections of unselected cell transistors being electrically connected.

Claim 25

A semiconductor integrated circuit device according to claim 20, wherein said spacers are insulating layers formed on said sidewall portions of said trenches.