US5608906A
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Multiple-task controller having a plurality of task memory input/output devices, input/output processing device, and a plurality of tasks controlled by external devices
Assignee: Nidec Instruments Corp
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Filing: 1994-06-23
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Granted: 1997-03-04
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Expires: 2014-06-23
Abstract
Abstract A multiple-task controller includes a plurality of tasks which are controlled with first and second external devices: task memory input/output devices provided respectively for the tasks; a serial input/output processing section and a parallel input/output processing section which process signals transmitted between the first and second external device and the input/output processing section, and perform writing and reading operations with respect to the task memory input/output devices; and a task control section which applies commands written in the task input/output devices respectively to the tasks, and applies the states of process of the tasks respectively to the task memory input/output devices.
Inventors
- 👤 Hiroshi Tonouchi
- 👤 Masashi Furukawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:03
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/042; G05B19/18; G05B19/414
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
94 words
A multiple-task controller comprising: a plurality of tasks controlled by external devices; a plurality of task memory input/output devices provided respectively for said tasks; input/output processing device for processing signals transmitted between said external devices and said input/output processing device, and for performing writing and reading operations between said input/output processing device and said task memory input/output devices; and a task control device for applying commands written in said task memory input/output devices respectively to said tasks, and for applying the states of process of said tasks respectively to said task memory input/output devices.
Claim 2
Dependent Claim
94 words
A multiple-task controller comprising: a plurality of tasks controlled by external devices; a plurality of task memory input/output devices provided respectively for said tasks; input/output processing device for processing signals transmitted between said external devices and said input/output processing device, and for performing writing and reading operations between said input/output processing device and said task memory input/output devices; and a task control device for applying commands written in said task memory input/output devices respectively to said tasks, and for applying the states of process of said tasks respectively to said task memory input/output devices.
Claim 3
Dependent Claim
62 words
A multiple-task controller as claimed in claim 1, wherein each of said task memory input/output devices includes: a task output section having bits to which predetermined control commands are assigned, for controlling a respective one of said plurality of tasks; and a task input section having bits to which predetermined state signals are assigned, for detecting the states of the respective task.
Claim 4
Dependent Claim
89 words
A multiple-task controller as claimed in claim 2, wherein said bits to which predetermined control commands are assigned comprise: a first bit which represents an error reset command; a second bit which represents a task initial start command; a third bit which represents a task continuation start command; a fourth bit which represents a task step start command; a fifth bit which represents a task cycle stop command; a sixth bit which represents a task step stop command; and a seventh output bit which represents a task hold command.
Claim 5
Dependent Claim
89 words
A multiple-task controller as claimed in claim 2, wherein said bits to which predetermined state signals are assigned comprise: a first bit which represents a kind of task; a second bit which represents an automatic-operation possible state; a third bit which represents a system error state; a fourth bit which represents a task being in an operation state; a fifth bit which represents a task cycle stop state; a sixth bit which represents a task step stop state; and a seventh bit which represents a task hold stop state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-03 | 2000-09-02 | 2001-03-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-03 | 2004-09-02 | 2005-03-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-03 | 2008-09-02 | 2009-03-04 | $7700.00 | Window Closed / Lapsed |