Synchronous semiconductor memory device with low power consumption

Claim 2

A synchronous semiconductor device comprising: an internal address generating means for generating an m(m=2, 3, . . . )-bit internal address which is successively changed; a memory section accessed by n(n<m) bits and having 2 m-n groups of internal data lines; 2 m-n groups of data input/output pins; M (M=1, 2, . . . )-bit input/output configuration memory device mode setting means for accessing said memory section by n bits of said m-bit internal address having smaller transition frequencies and for selecting one group of said 2 m-n groups of internal data lines by (m-n) bits of said m-bit internal address having larger transition frequencies to connect said selected group of internal data lines to one group of said 2 m-n groups of data input/output pins; and M×2 m-n -bit input/output configuration memory device mode setting means for accessing said memory section by n bits of said m-bit internal address having larger transition frequencies and for connecting said 2 m-n groups of internal data lines to said 2 m-n groups of data input/output pins.

Claim 3

A device as set forth in claim 1, wherein said internal address generating means receives a synchronization clock signal to increment said m-bit internal address by 1, said n bits of said m-bit internal address having smaller transition frequencies being higher n bits of said m-bit internal address, said (m-n) bits of said m-bit internal address having larger transition frequencies being lower (m-n) bits of said m-bit internal address, said n bits of said m-bit internal address having larger transition frequencies being lower n bits of said m-bit internal address.

Claim 4

A device as set forth in claim 1, wherein said internal address generating means receives a synchronization clock signal (SC)to decrement said m-bit internal address by 1, said n bits of said m-bit internal address having smaller transition frequencies being higher n bits of said m-bit internal address, said (m-n) bits of said m-bit internal address having larger transition frequencies being lower (m-n) bits of said m-bit internal address, said n bits of said m-bit internal address having larger transition frequencies being lower n bits of said m-bit internal address.

Claim 5

A device as set forth in claim 1, wherein said internal address generating means receives a synchronization clock signal to increment said m-bit internal address by 2, said n bits of said m-bit internal address having smaller transition frequencies being higher n bits of said m-bit internal address, and the least significant bit thereof, said (m-n) bits of said m-bit internal address having larger transition frequencies being lower (m-n) bits of said m-bit internal address except for the least significant bit thereof, said n bits of said m-bit internal address having larger transition frequencies being lower n bits of said m-bit internal address.

Claim 6

A device as set forth in claim 1, wherein said internal address generating means receives a synchronization clock signal to decrement said m-bit internal address by 2, said n bits of said m-bit internal address having smaller transition frequencies being higher n bits of said m-bit internal address and the least significant bit thereof, said (m-n) bits of said m-bit internal address having larger transition frequencies being lower (m-n) bits of said m-bit internal address except for the least significant bit thereof, said n bits of said m-bit internal address having larger transition frequencies being lower n bits of said m-bit internal address.

Claim 7

A device as set forth in claim 1, wherein said internal address generating means receives a synchronization clock signal to increment said m-bit internal address by 2 N-1 (N=3, 4, . . . ), said n bits of said m-bit internal address having smaller transition frequencies being higher n bits of said m-bit internal address and the least significant bits to the N-th least significant bits thereof, said (m-n) bits of said m-bit internal address having larger transition frequencies being lower (m-n) bits of said m-bit internal address except for the least significant bits to the N-th least significant bits thereof, said n bits of said m-bit internal address having larger transition frequencies being lower n bits of said m-bit internal address.

Claim 8

A device as set forth in claim 1, wherein said internal address generating means receives a synchronization clock signal to decrement said m-bit internal address by 2 N-1 (N=3, 4, . . . ), said n bits of said m-bit internal address having smaller transition frequencies being higher n bits of said m-bit internal address and the least significant bits to the N-th least significant bits thereof, said (m-n) bits of said m-bit internal address having larger transition frequencies being lower (m-n) bits of said m-bit internal address except for the least significant bits to the N-th least significant bits thereof, said n bits of said m-bit internal address having larger transition frequencies being lower n bits of said m-bit internal address.

Claim 9

A device as set forth in claim 1, wherein said internal address generating means receives a synchronization clock signal to change said m-bit internal address so that higher bits of said m-bit internal address have larger transition frequencies than lower bits of said m-bit internal address; said n bits of said m-bit internal address having smaller transition frequencies being lower n bits of said m-bit internal address, said (m-n) bits of said m-bit internal address having larger transition frequencies being higher (m-n) bits of said m-bit internal address, said n bits of said m-bit internal address laving larger transition frequencies being lower n bits of said m-bit internal address.

Claim 10

A synchronous semiconductor device comprising: an internal address generating means for generating an m (m=2, 3, . . . )-bit internal address which is successively changed; a memory section accessed by n(n<m) bits and having 2 m-n groups of internal data lines; 2 m-n groups of data input/output pins; M (M =1, 2, . . . )-bit input/output configuration memory device mode setting means for accessing said memory section by higher n bits of said m-bit internal address and for selecting one group of said 2 m-n groups of internal data lines by lower (m-n) bits of said m-bit internal address to connect said selected group of internal data lines to one group of said 2 m-n groups of data input/output pins; and M×2 m-n -bit input/output configuration memory device mode setting means for accessing said memory section by lower n bits of said m-bit internal address and for connecting said 2 m-n groups of internal data lines to said 2 m-n groups of data input/output pins.

Claim 11

A synchronous semiconductor device comprising: an internal address generating means for generating an m (m=2, 3, . . . )-bit internal address which is successively changed; a memory section accessed by n(n<m) bits and having 2 m-n groups of internal data lines; 2 m-n groups of data input/output pins; M (M =1, 2, . . . )-bit input/output configuration memory device mode setting means for accessing said memory section by higher n bits of said m-bit internal address and for selecting one group of said 2 m-n groups of internal data lines by lower (m-n) bits of said m-bit internal address to connect said selected group of internal data lines to one group of said 2 m-n groups of data input/output pins; and M×2 m-n -bit input/output configuration memory device mode setting means for accessing said memory section by lower n bits of said m-bit internal address and for connecting said 2 m-n groups of internal data lines to said 2 m-n groups of data input/output pins.

Claim 12

A synchronous semiconductor device comprising: an internal address generating means for generating an m (m=2, 3, . . . )-bit internal address which is successively changed; a memory section accessed by n (n<m) bits and having 2 m-n groups of internal data lines; .sup. m-n groups of data input/output pins; M (M=1, 2, . . . )-bit input/output configuration memory device mode setting means for accessing said memory section by lower n bits of said m-bit internal address and for selecting one group of said 2 m-n groups of internal data lines by higher (m-n) bits of said m-bit internal address to connect said selected group of internal data lines to one group of said 2 m-n groups of data input/output pins; and M×2 m-n -bit input/output configuration memory device mode setting means for accessing said memory section by higher n bits of said m-bit internal address and for connecting said 2 m-n groups of internal data lines to said 2 m-n groups of data input/output pins.

Claim 13

A synchronous semiconductor device comprising: an internal address generating means for generating an m (m=2, 3, . . . )-bit internal address which is successively changed; a memory section accessed by n (n<m) bits and having 2 m-n groups of internal data lines; .sup. m-n groups of data input/output pins; M (M=1, 2, . . . )-bit input/output configuration memory device mode setting means for accessing said memory section by lower n bits of said m-bit internal address and for selecting one group of said 2 m-n groups of internal data lines by higher (m-n) bits of said m-bit internal address to connect said selected group of internal data lines to one group of said 2 m-n groups of data input/output pins; and M×2 m-n -bit input/output configuration memory device mode setting means for accessing said memory section by higher n bits of said m-bit internal address and for connecting said 2 m-n groups of internal data lines to said 2 m-n groups of data input/output pins.

Claim 14

A synchronous semiconductor memory device comprising: an external address latch circuit for receiving a latch signal to latch an m-bit external address; a burst counter, connected to said external address latch circuit, for receiving a synchronization clock signal to generate an m-bit internal address based upon said external address; a memory section accessed by n (n<m) bits and having 2 m-n groups of internal data lines; 2 m-n groups of data input/output pins; an input/output selection means, connected between said 2 m-n groups of internal data lines and said 2 m-n groups of data input/output pins, for selecting one group of said 2 m-n groups of internal data lines for one of said 2 m-n groups of data input/output pins in an M (M=1, 2, . . . )-bit input/output configuration memory device mode and for connecting said 2 m-n groups of internal data lines to said 2 m-n groups of data input/output pins in an M×2 m-n -bit input/output configuration memory device mode; M (M =1, 2, . . . )-bit input/output configuration memory device mode setting means for accessing said memory section by n bits of said m-bit internal address having smaller transition frequencies and for activating said input/output selection means by supplying (m-n) bits of said m-bit internal address having larger transition frequencies; and M×2 m-n -bit input/output configuration memory device mode setting means for accessing said memory section by n bits of said m-bit internal address having larger transition frequencies and for deactivating said input/output selection means to connect said 2 m-n groups of internal data lines to said 2 m-n groups of data input/output pins.

Claim 15

A synchronous semiconductor memory device comprising: an external address latch circuit for receiving a latch signal to latch an m-bit external address; a burst counter, connected to said external address latch circuit, for receiving a synchronization clock signal to generate an m-bit internal address based upon said external address; a memory section accessed by n (n<m) bits and having 2 m-n groups of internal data lines; 2 m-n groups of data input/output pins; an input/output selection means, connected between said 2 m-n groups of internal data lines and said 2 m-n groups of data input/output pins, for selecting one group of said 2 m-n groups of internal data lines for one of said 2 m-n groups of data input/output pins in an M (M=1, 2, . . . )-bit input/output configuration memory device mode and for connecting said 2 m-n groups of internal data lines to said 2 m-n groups of data input/output pins in an M×2 m-n -bit input/output configuration memory device mode; M (M =1, 2, . . . )-bit input/output configuration memory device mode setting means for accessing said memory section by n bits of said m-bit internal address having smaller transition frequencies and for activating said input/output selection means by supplying (m-n) bits of said m-bit internal address having larger transition frequencies; and M×2 m-n -bit input/output configuration memory device mode setting means for accessing said memory section by n bits of said m-bit internal address having larger transition frequencies and for deactivating said input/output selection means to connect said 2 m-n groups of internal data lines to said 2 m-n groups of data input/output pins.

Claim 16

A device as set forth in claim 10, wherein said burst counter receives a synchronization clock signal to change said m-bit internal address by 2 n-1 (N=2, 3, . . . ), said n bits of said m-bit internal address having smaller transition frequencies being higher n bits of said m-bit internal address and the least significant bits to tile N-th least significant bits thereof, said (m-n) bits of said m-bit internal address having larger transition frequencies being lower (m-n) bits of said m-bit internal address except for the least significant bits to the N-th least significant bits thereof, said n bits of said m-bit internal address having larger transition frequencies being lower n bits of said m-bit internal address.

Claim 17

A synchronous semiconductor memory device comprising: an internal address generating means for generating an m-bit internal address in response to a synchronization clock signal; a memory section having 2 k groups of internal data lines, said memory section being capable of operating an M-bit input/output configuration memory device mode and an M×2 k (k=1, 2, . . . )-bit input/output configuration memory device mode, said 2 k groups of internal data lines selected by k bits of said m-bit internal address which bits are changed at a high frequency in response to said synchronization clock signal under said M-bit input/output configuration memory mode being equivalent to said 2 k groups of internal data lines under said M×2 k -bit input/output configuration memory mode.

Claim 18

A synchronous semiconductor memory device comprising: an internal address generating means for generating an m-bit internal address in response to a synchronization clock signal; a memory section having 2 k groups of internal data lines, said memory section being capable of operating an M-bit input/output configuration memory device mode and an M×2 k (k=1, 2, . . . )-bit input/output configuration memory device mode, said 2 k groups of internal data lines selected by k bits of said m-bit internal address which bits are changed at a high frequency in response to said synchronization clock signal under said M-bit input/output configuration memory mode being equivalent to said 2 k groups of internal data lines under said M×2 k -bit input/output configuration memory mode.